esp-idf/components/riscv/include/riscv
Li Shuai 9b99fc9033 cpu retention: software cpu retention support for esp32c6
cpu retention: add riscv core sleep critical and non-critical register layout structure definition

cpu retention: add assembly subroutine for cpu critical register backup and restore

cpu retention: add cpu core critical register context backup and restore support

cpu retention: add cpu core non-critical register context backup and restore support

cpu retention: add interrupt priority register context backup and restore support

cpu retention: add cache config register context backup and restore support

cpu retention: add plic interrupt register context backup and restore support

cpu retention: add clint interrupt register context backup and restore support

cpu retention: wait icache state idle before pmu enter sleep
2023-01-31 22:12:54 +08:00
..
csr.h esp32c6: Enable IRAM-DRAM split using PMP 2022-12-06 14:50:55 +00:00
encoding.h riscv: Add new arch-level component 2020-11-12 09:33:18 +11:00
instruction_decode.h interrupt: filter out reserved int number by decoding risc-v JAL instruction 2021-01-05 15:39:46 +08:00
interrupt.h riscv: Fix esprv_intc_int_set_threshold() naming 2022-09-16 16:45:43 +08:00
rv_utils.h esp_system: Minor update for esp32c6 2022-09-26 20:32:13 +08:00
rvruntime-frames.h riscv: Remove asm struct expressions in header files 2022-12-06 13:35:27 +03:00
rvsleep-frames.h cpu retention: software cpu retention support for esp32c6 2023-01-31 22:12:54 +08:00
semihosting.h semihosting: version 2 2022-05-05 09:12:42 +00:00