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https://github.com/espressif/esp-idf.git
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136 lines
4.7 KiB
C
136 lines
4.7 KiB
C
/**
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** XTS_AES_PLAIN_MEM register
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* The memory that stores plaintext
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*/
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#define XTS_AES_PLAIN_MEM (DR_REG_XTS_AES_BASE + 0x0)
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#define XTS_AES_PLAIN_MEM_SIZE_BYTES 16
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/** XTS_AES_LINESIZE_REG register
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* XTS-AES line-size register
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*/
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#define XTS_AES_LINESIZE_REG (DR_REG_XTS_AES_BASE + 0x40)
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/** XTS_AES_LINESIZE : R/W; bitpos: [0]; default: 0;
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* This bit stores the line size parameter. 0: 16Byte, 1: 32Byte.
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*/
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#define XTS_AES_LINESIZE (BIT(0))
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#define XTS_AES_LINESIZE_M (XTS_AES_LINESIZE_V << XTS_AES_LINESIZE_S)
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#define XTS_AES_LINESIZE_V 0x00000001U
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#define XTS_AES_LINESIZE_S 0
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/** XTS_AES_DESTINATION_REG register
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* XTS-AES destination register
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*/
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#define XTS_AES_DESTINATION_REG (DR_REG_XTS_AES_BASE + 0x44)
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/** XTS_AES_DESTINATION : R/W; bitpos: [0]; default: 0;
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* This bit stores the destination. 0: flash(default). 1: reserved.
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*/
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#define XTS_AES_DESTINATION (BIT(0))
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#define XTS_AES_DESTINATION_M (XTS_AES_DESTINATION_V << XTS_AES_DESTINATION_S)
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#define XTS_AES_DESTINATION_V 0x00000001U
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#define XTS_AES_DESTINATION_S 0
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/** XTS_AES_PHYSICAL_ADDRESS_REG register
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* XTS-AES physical address register
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*/
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#define XTS_AES_PHYSICAL_ADDRESS_REG (DR_REG_XTS_AES_BASE + 0x48)
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/** XTS_AES_PHYSICAL_ADDRESS : R/W; bitpos: [29:0]; default: 0;
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* Those bits stores the physical address. If linesize is 16-byte, the physical
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* address should be aligned of 16 bytes. If linesize is 32-byte, the physical address
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* should be aligned of 32 bytes.
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*/
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#define XTS_AES_PHYSICAL_ADDRESS 0x3FFFFFFFU
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#define XTS_AES_PHYSICAL_ADDRESS_M (XTS_AES_PHYSICAL_ADDRESS_V << XTS_AES_PHYSICAL_ADDRESS_S)
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#define XTS_AES_PHYSICAL_ADDRESS_V 0x3FFFFFFFU
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#define XTS_AES_PHYSICAL_ADDRESS_S 0
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/** XTS_AES_TRIGGER_REG register
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* XTS-AES trigger register
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*/
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#define XTS_AES_TRIGGER_REG (DR_REG_XTS_AES_BASE + 0x4c)
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/** XTS_AES_TRIGGER : WT; bitpos: [0]; default: 0;
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* Set this bit to start manual encryption calculation
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*/
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#define XTS_AES_TRIGGER (BIT(0))
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#define XTS_AES_TRIGGER_M (XTS_AES_TRIGGER_V << XTS_AES_TRIGGER_S)
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#define XTS_AES_TRIGGER_V 0x00000001U
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#define XTS_AES_TRIGGER_S 0
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/** XTS_AES_RELEASE_REG register
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* XTS-AES release register
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*/
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#define XTS_AES_RELEASE_REG (DR_REG_XTS_AES_BASE + 0x50)
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/** XTS_AES_RELEASE : WT; bitpos: [0]; default: 0;
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* Set this bit to release the manual encrypted result, after that the result will be
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* visible to spi
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*/
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#define XTS_AES_RELEASE (BIT(0))
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#define XTS_AES_RELEASE_M (XTS_AES_RELEASE_V << XTS_AES_RELEASE_S)
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#define XTS_AES_RELEASE_V 0x00000001U
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#define XTS_AES_RELEASE_S 0
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/** XTS_AES_DESTROY_REG register
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* XTS-AES destroy register
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*/
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#define XTS_AES_DESTROY_REG (DR_REG_XTS_AES_BASE + 0x54)
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/** XTS_AES_DESTROY : WT; bitpos: [0]; default: 0;
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* Set this bit to destroy XTS-AES result.
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*/
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#define XTS_AES_DESTROY (BIT(0))
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#define XTS_AES_DESTROY_M (XTS_AES_DESTROY_V << XTS_AES_DESTROY_S)
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#define XTS_AES_DESTROY_V 0x00000001U
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#define XTS_AES_DESTROY_S 0
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/** XTS_AES_STATE_REG register
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* XTS-AES status register
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*/
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#define XTS_AES_STATE_REG (DR_REG_XTS_AES_BASE + 0x58)
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/** XTS_AES_STATE : RO; bitpos: [1:0]; default: 0;
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* Those bits shows XTS-AES status. 0=IDLE, 1=WORK, 2=RELEASE, 3=USE. IDLE means that
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* XTS-AES is idle. WORK means that XTS-AES is busy with calculation. RELEASE means
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* the encrypted result is generated but not visible to mspi. USE means that the
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* encrypted result is visible to mspi.
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*/
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#define XTS_AES_STATE 0x00000003U
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#define XTS_AES_STATE_M (XTS_AES_STATE_V << XTS_AES_STATE_S)
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#define XTS_AES_STATE_V 0x00000003U
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#define XTS_AES_STATE_S 0
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/** XTS_AES_DATE_REG register
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* XTS-AES version control register
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*/
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#define XTS_AES_DATE_REG (DR_REG_XTS_AES_BASE + 0x5c)
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/** XTS_AES_DATE : R/W; bitpos: [29:0]; default: 538969635;
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* Those bits stores the version information of XTS-AES.
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*/
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#define XTS_AES_DATE 0x3FFFFFFFU
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#define XTS_AES_DATE_M (XTS_AES_DATE_V << XTS_AES_DATE_S)
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#define XTS_AES_DATE_V 0x3FFFFFFFU
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#define XTS_AES_DATE_S 0
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/* For backward compatability with the older register names */
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#define AES_XTS_PLAIN_BASE XTS_AES_PLAIN_MEM
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#define AES_XTS_SIZE_REG XTS_AES_LINESIZE_REG
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#define AES_XTS_DESTINATION_REG XTS_AES_DESTINATION_REG
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#define AES_XTS_PHYSICAL_ADDR_REG XTS_AES_PHYSICAL_ADDRESS_REG
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#define AES_XTS_TRIGGER_REG XTS_AES_TRIGGER_REG
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#define AES_XTS_RELEASE_REG XTS_AES_RELEASE_REG
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#define AES_XTS_DESTROY_REG XTS_AES_DESTROY_REG
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#define AES_XTS_STATE_REG XTS_AES_STATE_REG
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#define AES_XTS_DATE_REG XTS_AES_DATE_REG
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#ifdef __cplusplus
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}
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#endif
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