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5b516b107a
timer group interrupt enable is controled by level_int_ena instead of int_ena Closes https://github.com/espressif/esp-idf/issues/5103
574 lines
16 KiB
C
574 lines
16 KiB
C
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// The LL layer for Timer Group register operations.
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// Note that most of the register operations in this layer are non-atomic operations.
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdlib.h>
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#include "hal/timer_types.h"
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#include "soc/timer_periph.h"
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_Static_assert(TIMER_INTR_T0 == TIMG_T0_INT_CLR, "Add mapping to LL interrupt handling, since it's no longer naturally compatible with the timer_intr_t");
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_Static_assert(TIMER_INTR_T1 == TIMG_T1_INT_CLR, "Add mapping to LL interrupt handling, since it's no longer naturally compatible with the timer_intr_t");
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_Static_assert(TIMER_INTR_WDT == TIMG_WDT_INT_CLR, "Add mapping to LL interrupt handling, since it's no longer naturally compatible with the timer_intr_t");
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// Get timer group instance with giving group number
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#define TIMER_LL_GET_HW(num) ((num == 0) ? (&TIMERG0) : (&TIMERG1))
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/**
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* @brief Set timer clock prescale value
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*
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* @param hw Beginning address of the peripheral registers.
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* @param timer_num The timer number
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* @param divider Prescale value (0 is not valid)
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*
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* @return None
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*/
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static inline void timer_ll_set_divider(timg_dev_t *hw, timer_idx_t timer_num, uint32_t divider)
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{
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// refer to TRM 12.2.1
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if (divider == 65536) {
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divider = 0;
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}
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int timer_en = hw->hw_timer[timer_num].config.enable;
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hw->hw_timer[timer_num].config.enable = 0;
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hw->hw_timer[timer_num].config.divider = divider;
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hw->hw_timer[timer_num].config.enable = timer_en;
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}
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/**
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* @brief Get timer clock prescale value
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*
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* @param hw Beginning address of the peripheral registers.
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* @param timer_num The timer number
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* @param divider Pointer to accept the prescale value
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*
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* @return None
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*/
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static inline void timer_ll_get_divider(timg_dev_t *hw, timer_idx_t timer_num, uint32_t *divider)
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{
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uint32_t d = hw->hw_timer[timer_num].config.divider;
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if (d == 0) {
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d = 65536;
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}
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*divider = d;
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}
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/**
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* @brief Load counter value into time-base counter
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*
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* @param hw Beginning address of the peripheral registers.
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* @param timer_num The timer number
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* @param load_val Counter value
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*
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* @return None
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*/
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static inline void timer_ll_set_counter_value(timg_dev_t *hw, timer_idx_t timer_num, uint64_t load_val)
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{
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hw->hw_timer[timer_num].load_high = (uint32_t) (load_val >> 32);
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hw->hw_timer[timer_num].load_low = (uint32_t) load_val;
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hw->hw_timer[timer_num].reload = 1;
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}
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/**
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* @brief Get counter value from time-base counter
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*
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* @param hw Beginning address of the peripheral registers.
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* @param timer_num The timer number
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* @param timer_val Pointer to accept the counter value
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*
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* @return None
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*/
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FORCE_INLINE_ATTR void timer_ll_get_counter_value(timg_dev_t *hw, timer_idx_t timer_num, uint64_t *timer_val)
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{
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hw->hw_timer[timer_num].update.update = 1;
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*timer_val = ((uint64_t) hw->hw_timer[timer_num].cnt_high << 32) | (hw->hw_timer[timer_num].cnt_low);
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}
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/**
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* @brief Set counter mode, include increment mode and decrement mode.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param timer_num The timer number
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* @param increase_en True to increment mode, fasle to decrement mode
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*
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* @return None
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*/
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static inline void timer_ll_set_counter_increase(timg_dev_t *hw, timer_idx_t timer_num, bool increase_en)
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{
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hw->hw_timer[timer_num].config.increase = increase_en;
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}
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/**
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* @brief Get counter mode, include increment mode and decrement mode.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param timer_num The timer number
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*
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* @return
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* - true Increment mode
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* - false Decrement mode
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*/
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static inline bool timer_ll_get_counter_increase(timg_dev_t *hw, timer_idx_t timer_num)
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{
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return hw->hw_timer[timer_num].config.increase;
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}
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/**
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* @brief Set counter status, enable or disable counter.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param timer_num The timer number
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* @param counter_en True to enable counter, false to disable counter
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*
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* @return None
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*/
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FORCE_INLINE_ATTR void timer_ll_set_counter_enable(timg_dev_t *hw, timer_idx_t timer_num, bool counter_en)
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{
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hw->hw_timer[timer_num].config.enable = counter_en;
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}
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/**
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* @brief Get counter status.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param timer_num The timer number
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*
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* @return
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* - true Enable counter
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* - false Disable conuter
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*/
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static inline bool timer_ll_get_counter_enable(timg_dev_t *hw, timer_idx_t timer_num)
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{
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return hw->hw_timer[timer_num].config.enable;
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}
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/**
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* @brief Set auto reload mode.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param timer_num The timer number
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* @param auto_reload_en True to enable auto reload mode, flase to disable auto reload mode
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*
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* @return None
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*/
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static inline void timer_ll_set_auto_reload(timg_dev_t *hw, timer_idx_t timer_num, bool auto_reload_en)
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{
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hw->hw_timer[timer_num].config.autoreload = auto_reload_en;
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}
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/**
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* @brief Get auto reload mode.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param timer_num The timer number
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*
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* @return
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* - true Enable auto reload mode
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* - false Disable auto reload mode
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*/
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FORCE_INLINE_ATTR bool timer_ll_get_auto_reload(timg_dev_t *hw, timer_idx_t timer_num)
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{
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return hw->hw_timer[timer_num].config.autoreload;
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}
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/**
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* @brief Set the counter value to trigger the alarm.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param timer_num The timer number
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* @param alarm_value Counter value to trigger the alarm
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*
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* @return None
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*/
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FORCE_INLINE_ATTR void timer_ll_set_alarm_value(timg_dev_t *hw, timer_idx_t timer_num, uint64_t alarm_value)
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{
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hw->hw_timer[timer_num].alarm_high = (uint32_t) (alarm_value >> 32);
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hw->hw_timer[timer_num].alarm_low = (uint32_t) alarm_value;
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}
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/**
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* @brief Get the counter value to trigger the alarm.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param timer_num The timer number
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* @param alarm_value Pointer to accept the counter value to trigger the alarm
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*
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* @return None
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*/
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static inline void timer_ll_get_alarm_value(timg_dev_t *hw, timer_idx_t timer_num, uint64_t *alarm_value)
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{
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*alarm_value = ((uint64_t) hw->hw_timer[timer_num].alarm_high << 32) | (hw->hw_timer[timer_num].alarm_low);
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}
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/**
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* @brief Set the alarm status, enable or disable the alarm.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param timer_num The timer number
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* @param alarm_en True to enable alarm, false to disable alarm
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*
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* @return None
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*/
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FORCE_INLINE_ATTR void timer_ll_set_alarm_enable(timg_dev_t *hw, timer_idx_t timer_num, bool alarm_en)
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{
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hw->hw_timer[timer_num].config.alarm_en = alarm_en;
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}
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/**
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* @brief Get the alarm status.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param timer_num The timer number
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*
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* @return
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* - true Enable alarm
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* - false Disable alarm
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*/
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static inline bool timer_ll_get_alarm_enable(timg_dev_t *hw, timer_idx_t timer_num)
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{
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return hw->hw_timer[timer_num].config.alarm_en;
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}
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/**
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* @brief Enable timer interrupt.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param timer_num The timer number
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*
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* @return None
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*/
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FORCE_INLINE_ATTR void timer_ll_intr_enable(timg_dev_t *hw, timer_idx_t timer_num)
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{
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hw->int_ena.val |= BIT(timer_num);
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hw->hw_timer[timer_num].config.level_int_en = 1;
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}
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/**
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* @brief Disable timer interrupt.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param timer_num The timer number
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*
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* @return None
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*/
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FORCE_INLINE_ATTR void timer_ll_intr_disable(timg_dev_t *hw, timer_idx_t timer_num)
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{
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hw->int_ena.val &= (~BIT(timer_num));
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hw->hw_timer[timer_num].config.level_int_en = 0;
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}
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/**
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* @brief Disable timer interrupt.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param timer_num The timer number
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*
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* @return None
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*/
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FORCE_INLINE_ATTR void timer_ll_clear_intr_status(timg_dev_t *hw, timer_idx_t timer_num)
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{
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hw->int_clr.val |= BIT(timer_num);
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}
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/**
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* @brief Get interrupt status.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param intr_status Interrupt status
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*
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* @return None
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*/
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FORCE_INLINE_ATTR void timer_ll_get_intr_status(timg_dev_t *hw, uint32_t *intr_status)
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{
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*intr_status = hw->int_st.val;
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}
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/**
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* @brief Get interrupt raw status.
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*
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* @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
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* @param intr_raw_status Interrupt raw status
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*
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* @return None
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*/
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FORCE_INLINE_ATTR void timer_ll_get_intr_raw_status(timer_group_t group_num, uint32_t *intr_raw_status)
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{
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timg_dev_t *hw = TIMER_LL_GET_HW(group_num);
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*intr_raw_status = hw->int_raw.val;
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}
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/**
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* @brief Set the level interrupt status, enable or disable the level interrupt.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param timer_num The timer number
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* @param level_int_en True to enable level interrupt, false to disable level interrupt
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*
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* @return None
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*/
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static inline void timer_ll_set_level_int_enable(timg_dev_t *hw, timer_idx_t timer_num, bool level_int_en)
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{
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hw->hw_timer[timer_num].config.level_int_en = level_int_en;
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}
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/**
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* @brief Get the level interrupt status.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param timer_num The timer number
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*
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* @return
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* - true Enable level interrupt
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* - false Disable level interrupt
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*/
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static inline bool timer_ll_get_level_int_enable(timg_dev_t *hw, timer_idx_t timer_num)
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{
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return hw->hw_timer[timer_num].config.level_int_en;
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}
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/**
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* @brief Set the edge interrupt status, enable or disable the edge interrupt.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param timer_num The timer number
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* @param edge_int_en True to enable edge interrupt, false to disable edge interrupt
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*
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* @return None
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*/
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static inline void timer_ll_set_edge_int_enable(timg_dev_t *hw, timer_idx_t timer_num, bool edge_int_en)
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{
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hw->hw_timer[timer_num].config.edge_int_en = edge_int_en;
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}
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/**
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* @brief Get the edge interrupt status.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param timer_num The timer number
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*
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* @return
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* - true Enable edge interrupt
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* - false Disable edge interrupt
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*/
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static inline bool timer_ll_get_edge_int_enable(timg_dev_t *hw, timer_idx_t timer_num)
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{
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return hw->hw_timer[timer_num].config.edge_int_en;
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}
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/**
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* @brief Get interrupt status register address.
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*
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* @param hw Beginning address of the peripheral registers.
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*
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* @return uint32_t Interrupt status register address
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*/
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static inline uint32_t timer_ll_get_intr_status_reg(timg_dev_t *hw)
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{
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return (uint32_t) & (hw->int_st.val);
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}
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static inline uint32_t timer_ll_get_intr_mask_bit(timg_dev_t *hw, timer_idx_t timer_num)
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{
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return (1U << timer_num);
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}
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/**
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* @brief Set clock source.
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*
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* @param hal Context of the HAL layer
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* @param use_xtal_en True to use XTAL clock, flase to use APB clock
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*
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* @return None
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*/
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static inline void timer_ll_set_use_xtal(timg_dev_t *hw, timer_idx_t timer_num, bool use_xtal_en)
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{
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hw->hw_timer[timer_num].config.use_xtal = use_xtal_en;
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}
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/**
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* @brief Get clock source.
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*
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* @param hal Context of the HAL layer
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*
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* @return
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* - true Use XTAL clock
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* - false Use APB clock
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*/
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static inline bool timer_ll_get_use_xtal(timg_dev_t *hw, timer_idx_t timer_num)
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{
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return hw->hw_timer[timer_num].config.use_xtal;
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}
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/* WDT operations */
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/**
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* @brief Unlock/lock the WDT register in case of mis-operations.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param protect true to lock, false to unlock before operations.
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*/
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FORCE_INLINE_ATTR void timer_ll_wdt_set_protect(timg_dev_t* hw, bool protect)
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{
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hw->wdt_wprotect=(protect? 0: TIMG_WDT_WKEY_VALUE);
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}
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/**
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* @brief Initialize WDT.
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*
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* @param hw Beginning address of the peripheral registers.
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*
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* @note Call `timer_ll_wdt_set_protect` first
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*/
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FORCE_INLINE_ATTR void timer_ll_wdt_init(timg_dev_t* hw)
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{
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hw->wdt_config0.sys_reset_length=7; //3.2uS
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hw->wdt_config0.cpu_reset_length=7; //3.2uS
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//currently only level interrupt is supported
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hw->wdt_config0.level_int_en = 1;
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hw->wdt_config0.edge_int_en = 0;
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}
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/**
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* @brief Set the WDT tick time.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param tick_time_us Tick time.
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*/
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FORCE_INLINE_ATTR void timer_ll_wdt_set_tick(timg_dev_t* hw, int tick_time_us)
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{
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hw->wdt_config1.clk_prescale=80*tick_time_us;
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}
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/**
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* @brief Feed the WDT.
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*
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* @param hw Beginning address of the peripheral registers.
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*/
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FORCE_INLINE_ATTR void timer_ll_wdt_feed(timg_dev_t* hw)
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{
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hw->wdt_feed = 1;
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}
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/**
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* @brief Set the WDT timeout.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param stage Stage number of WDT.
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* @param timeout_Tick tick threshold of timeout.
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*/
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FORCE_INLINE_ATTR void timer_ll_wdt_set_timeout(timg_dev_t* hw, int stage, uint32_t timeout_tick)
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{
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switch (stage) {
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case 0:
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hw->wdt_config2=timeout_tick;
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break;
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case 1:
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hw->wdt_config3=timeout_tick;
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break;
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case 2:
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hw->wdt_config4=timeout_tick;
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break;
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case 3:
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hw->wdt_config5=timeout_tick;
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break;
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default:
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abort();
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}
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}
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_Static_assert(TIMER_WDT_OFF == TIMG_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with the timer_wdt_behavior_t");
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_Static_assert(TIMER_WDT_INT == TIMG_WDT_STG_SEL_INT, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with the timer_wdt_behavior_t");
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|
_Static_assert(TIMER_WDT_RESET_CPU == TIMG_WDT_STG_SEL_RESET_CPU, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with the timer_wdt_behavior_t");
|
|
_Static_assert(TIMER_WDT_RESET_SYSTEM == TIMG_WDT_STG_SEL_RESET_SYSTEM, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with the timer_wdt_behavior_t");
|
|
|
|
/**
|
|
* @brief Set the WDT timeout behavior.
|
|
*
|
|
* @param hw Beginning address of the peripheral registers.
|
|
* @param stage Stage number of WDT.
|
|
* @param behavior Behavior of WDT, please see enum timer_wdt_behavior_t.
|
|
*/
|
|
FORCE_INLINE_ATTR void timer_ll_wdt_set_timeout_behavior(timg_dev_t* hw, int stage, timer_wdt_behavior_t behavior)
|
|
{
|
|
switch (stage) {
|
|
case 0:
|
|
hw->wdt_config0.stg0 = behavior;
|
|
break;
|
|
case 1:
|
|
hw->wdt_config0.stg1 = behavior;
|
|
break;
|
|
case 2:
|
|
hw->wdt_config0.stg2 = behavior;
|
|
break;
|
|
case 3:
|
|
hw->wdt_config0.stg3 = behavior;
|
|
break;
|
|
default:
|
|
abort();
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Enable/Disable the WDT enable.
|
|
*
|
|
* @param hw Beginning address of the peripheral registers.
|
|
* @param enable True to enable WDT, false to disable WDT.
|
|
*/
|
|
FORCE_INLINE_ATTR void timer_ll_wdt_set_enable(timg_dev_t* hw, bool enable)
|
|
{
|
|
hw->wdt_config0.en = enable;
|
|
}
|
|
|
|
/**
|
|
* @brief Enable/Disable the WDT flashboot mode.
|
|
*
|
|
* @param hw Beginning address of the peripheral registers.
|
|
* @param enable True to enable WDT flashboot mode, false to disable WDT flashboot mode.
|
|
*/
|
|
FORCE_INLINE_ATTR void timer_ll_wdt_flashboot_en(timg_dev_t* hw, bool enable)
|
|
{
|
|
hw->wdt_config0.flashboot_mod_en = enable;
|
|
}
|
|
|
|
/**
|
|
* @brief Clear the WDT interrupt status.
|
|
*
|
|
* @param hw Beginning address of the peripheral registers.
|
|
*/
|
|
FORCE_INLINE_ATTR void timer_ll_wdt_clear_intr_status(timg_dev_t* hw)
|
|
{
|
|
hw->int_clr.wdt = 1;
|
|
}
|
|
|
|
/**
|
|
* @brief Enable the WDT interrupt.
|
|
*
|
|
* @param hw Beginning address of the peripheral registers.
|
|
*/
|
|
FORCE_INLINE_ATTR void timer_ll_wdt_enable_intr(timg_dev_t* hw)
|
|
{
|
|
hw->int_ena.wdt = 1;
|
|
}
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|