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563 lines
16 KiB
ArmAsm
563 lines
16 KiB
ArmAsm
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <xtensa/coreasm.h>
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#include <xtensa/corebits.h>
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#include <xtensa/config/system.h>
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#include "freertos/xtensa_context.h"
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#include "freertos/xtensa_rtos.h"
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#include "esp_panic.h"
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#include "sdkconfig.h"
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#include "soc/soc.h"
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#include "soc/dport_reg.h"
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#include "soc/timer_group_reg.h"
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/*
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Interrupt , a high-priority interrupt, is used for several things:
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- Dport access mediation
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- Cache error panic handler
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- Interrupt watchdog panic handler
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*/
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#define L5_INTR_STACK_SIZE 12
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#define L5_INTR_A2_OFFSET 0
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#define L5_INTR_A3_OFFSET 4
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#define L5_INTR_A4_OFFSET 8
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.data
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_l5_intr_stack:
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.space L5_INTR_STACK_SIZE*portNUM_PROCESSORS
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#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
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.global _l5_intr_livelock_counter
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.global _l5_intr_livelock_max
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.align 16
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_l5_intr_livelock_counter:
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.word 0
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_l5_intr_livelock_max:
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.word 0
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_l5_intr_livelock_sync:
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.word 0, 0
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_l5_intr_livelock_app:
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.word 0
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_l5_intr_livelock_pro:
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.word 0
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#endif
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.section .iram1,"ax"
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.global xt_highint5
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.type xt_highint5,@function
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.align 4
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xt_highint5:
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#ifndef CONFIG_FREERTOS_UNICORE
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/* See if we're here for the dport access interrupt */
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rsr a0, INTERRUPT
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extui a0, a0, ETS_DPORT_INUM, 1
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bnez a0, .handle_dport_access_int
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#endif // CONFIG_FREERTOS_UNICORE
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#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
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/* Timer 2 interrupt */
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rsr a0, INTENABLE
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extui a0, a0, 16, 1
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beqz a0, 1f
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rsr a0, INTERRUPT
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extui a0, a0, 16, 1
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bnez a0, .handle_multicore_debug_int
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1:
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/* See if we're here for the tg1 watchdog interrupt */
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rsr a0, INTERRUPT
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extui a0, a0, ETS_T1_WDT_INUM, 1
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beqz a0, 1f
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/* Pro cpu (Core 0) can execute to here. */
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wsr a5, depc /* use DEPC as temp storage */
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movi a0, _l5_intr_livelock_counter
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l32i a0, a0, 0
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movi a5, _l5_intr_livelock_max
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l32i a5, a5, 0
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bltu a0, a5, .handle_livelock_int /* _l5_intr_livelock_counter < _l5_intr_livelock_max */
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rsr a5, depc /* restore a5 */
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#endif
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/* Allocate exception frame and save minimal context. */
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1: mov a0, sp
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addi sp, sp, -XT_STK_FRMSZ
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s32i a0, sp, XT_STK_A1
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#if XCHAL_HAVE_WINDOWED
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s32e a0, sp, -12 /* for debug backtrace */
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#endif
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rsr a0, PS /* save interruptee's PS */
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s32i a0, sp, XT_STK_PS
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rsr a0, EPC_5 /* save interruptee's PC */
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s32i a0, sp, XT_STK_PC
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#if XCHAL_HAVE_WINDOWED
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s32e a0, sp, -16 /* for debug backtrace */
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#endif
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s32i a12, sp, XT_STK_A12 /* _xt_context_save requires A12- */
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s32i a13, sp, XT_STK_A13 /* A13 to have already been saved */
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call0 _xt_context_save
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/* Save vaddr into exception frame */
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rsr a0, EXCVADDR
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s32i a0, sp, XT_STK_EXCVADDR
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/* Figure out reason, save into EXCCAUSE reg */
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rsr a0, INTERRUPT
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extui a0, a0, ETS_CACHEERR_INUM, 1 /* get cacheerr int bit */
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beqz a0, 1f
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/* Kill this interrupt; we cannot reset it. */
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rsr a0, INTENABLE
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movi a4, ~(1<<ETS_CACHEERR_INUM)
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and a0, a4, a0
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wsr a0, INTENABLE
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movi a0, PANIC_RSN_CACHEERR
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j 9f
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1:
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#if CONFIG_INT_WDT_CHECK_CPU1
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/* Check if the cause is the app cpu failing to tick.*/
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movi a0, int_wdt_app_cpu_ticked
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l32i a0, a0, 0
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bnez a0, 2f
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/* It is. Modify cause. */
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movi a0,PANIC_RSN_INTWDT_CPU1
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j 9f
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2:
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#endif
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/* Set EXCCAUSE to reflect cause of the wdt int trigger */
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movi a0,PANIC_RSN_INTWDT_CPU0
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9:
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/* Found the reason, now save it. */
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s32i a0, sp, XT_STK_EXCCAUSE
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/* _xt_context_save seems to save the current a0, but we need the interuptees a0. Fix this. */
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rsr a0, EXCSAVE_5 /* save interruptee's a0 */
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s32i a0, sp, XT_STK_A0
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/* Set up PS for C, disable all interrupts except NMI and debug, and clear EXCM. */
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movi a0, PS_INTLEVEL(5) | PS_UM | PS_WOE
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wsr a0, PS
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//Call panic handler
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mov a6,sp
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call4 panicHandler
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call0 _xt_context_restore
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l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */
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wsr a0, PS
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l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */
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wsr a0, EPC_5
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l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */
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l32i sp, sp, XT_STK_A1 /* remove exception frame */
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rsync /* ensure PS and EPC written */
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rsr a0, EXCSAVE_5 /* restore a0 */
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rfi 5
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#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
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#define APB_ITCTRL (0x3f00)
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#define APB_DCRSET (0x200c)
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#define ERI_ADDR(APB) (0x100000 + (APB))
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.align 4
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.handle_multicore_debug_int:
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wsr a2, depc /* temp storage */
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rsr.ccount a2
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addmi a2, a2, (CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ*50)
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wsr a2, CCOMPARE2
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/* Enable Integration Mode */
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movi a2, ERI_ADDR(APB_ITCTRL)
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rer a0, a2
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addi a0, a0, 1
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wer a0, a2
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/* Enable and emit BreakOut signal */
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movi a2, ERI_ADDR(APB_DCRSET)
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rer a0, a2
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movi a2, 0x1020000
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or a0, a2, a0
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movi a2, ERI_ADDR(APB_DCRSET)
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wer a0, a2
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.rept 4
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nop
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.endr
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/* Disable Normally Mode */
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movi a2, ERI_ADDR(APB_ITCTRL)
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rer a0, a2
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movi a2, ~0x1
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and a0, a2, a0
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movi a2, ERI_ADDR(APB_ITCTRL)
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wer a0, a2
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rsr a2, depc
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rsr a0, EXCSAVE_5 /* restore a0 */
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rfi 5
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/*
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--------------------------------------------------------------------------------
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Macro intr_matrix_map - Attach an CPU interrupt to a hardware source.
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Input : "addr" - Interrupt map configuration base address
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Input : "src" - Interrupt source.
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Input : "inum" - Interrupt number.
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--------------------------------------------------------------------------------
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*/
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.macro intr_matrix_map addr src inum
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movi a2, \src
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slli a2, a2, 2
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movi a3, \addr
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add a3, a3, a2
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movi a2, \inum
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s32i a2, a3, 0
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memw
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.endm
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/*
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--------------------------------------------------------------------------------
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Macro wdt_clr_intr_status - Clear the WDT interrupt status.
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Macro wdt_feed - Feed the WDT.
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Input : "dev" - Beginning address of the peripheral registers
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--------------------------------------------------------------------------------
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*/
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.macro wdt_clr_intr_status dev
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movi a2, \dev
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movi a3, TIMG_WDT_WKEY_VALUE
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s32i a3, a2, 100 /* disable write protect */
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memw
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l32i a4, a2, 164
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memw
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movi a3, 4
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or a3, a4, a3
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s32i a3, a2, 164 /* clear 1st stage timeout interrupt */
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memw
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movi a3, 0
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s32i a3, a2, 100 /* enable write protect */
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memw
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.endm
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.macro wdt_feed dev
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movi a2, \dev
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movi a3, TIMG_WDT_WKEY_VALUE
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s32i a3, a2, 100 /* disable write protect */
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memw
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movi a4, _l5_intr_livelock_max
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l32i a4, a4, 0
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memw
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addi a4, a4, 1
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movi a3, (CONFIG_INT_WDT_TIMEOUT_MS<<1)
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quou a3, a3, a4
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s32i a3, a2, 80 /* set timeout before interrupt */
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memw
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movi a3, (CONFIG_INT_WDT_TIMEOUT_MS<<2)
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s32i a3, a2, 84 /* set timeout before system reset */
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memw
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movi a3, 1
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s32i a3, a2, 96 /* feed wdt */
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memw
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movi a3, 0
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s32i a3, a2, 100 /* enable write protect */
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memw
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.endm
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.align 4
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.handle_livelock_int:
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movi a0, SOC_RTC_DATA_LOW
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movi a5, _l5_intr_livelock_sync
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l32i a5, a5, 0
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s32i a5, a0, 0
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memw
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movi a5, _l5_intr_livelock_sync
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l32i a5, a5, 4
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s32i a5, a0, 4
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memw
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movi a5, _l5_intr_livelock_app
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l32i a5, a5, 0
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s32i a5, a0, 8
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memw
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movi a5, _l5_intr_livelock_counter
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l32i a5, a5, 0
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s32i a5, a0, 12
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memw
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getcoreid a5
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/* Save A2, A3, A4 so we can use those registers */
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movi a0, L5_INTR_STACK_SIZE
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mull a5, a5, a0
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movi a0, _l5_intr_stack
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add a0, a0, a5
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s32i a2, a0, L5_INTR_A2_OFFSET
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s32i a3, a0, L5_INTR_A3_OFFSET
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s32i a4, a0, L5_INTR_A4_OFFSET
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/* Here, we can use a0, a2, a3, a4, a5 registers */
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getcoreid a5
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beqz a5, 1f
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movi a2, _l5_intr_livelock_app
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l32i a3, a2, 0
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addi a3, a3, 1
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s32i a3, a2, 0
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/* Dual core synchronization, ensuring that both cores enter interrupts */
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1: movi a4, 0x1
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movi a2, _l5_intr_livelock_sync
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addx4 a3, a5, a2
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s32i a4, a3, 0
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1: movi a2, _l5_intr_livelock_sync
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movi a3, 1
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addx4 a3, a3, a2
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l32i a2, a2, 0
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l32i a3, a3, 0
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and a2, a2, a3
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beqz a2, 1b
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rsil a0, CONFIG_ESP32_DPORT_DIS_INTERRUPT_LVL /* disable nested interrupt */
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beqz a5, 1f /* Pro cpu (Core 0) jump bypass */
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movi a2, _l5_intr_livelock_app
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l32i a2, a2, 0
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bnei a2, 2, 1f
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movi a2, _l5_intr_livelock_counter /* _l5_intr_livelock_counter++ */
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l32i a3, a2, 0
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addi a3, a3, 1
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s32i a3, a2, 0
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/*
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The delay time can be calculated by the following formula:
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T = ceil(0.25 + max(t1, t2)) us
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t1 = 80 / f1, t2 = (1 + 14/N) * 20 / f2
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f1: PSRAM access frequency, unit: MHz.
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f2: Flash access frequency, unit: MHz.
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When flash is slow/fast read, N = 1.
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When flash is DOUT/DIO read, N = 2.
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When flash is QOUT/QIO read, N = 4.
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*/
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1: rsr.ccount a2
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movi a3, g_ticks_per_us_pro
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movi a4, g_ticks_per_us_app
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moveqz a4, a3, a5
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l32i a4, a4, 0
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#if defined(CONFIG_FLASHMODE_QIO) || defined(CONFIG_FLASHMODE_QOUT)
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# if defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_80M)
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movi a3, 2
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# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_40M)
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movi a3, 3
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# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_40M) && defined(CONFIG_SPIRAM_SPEED_40M)
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movi a3, 3
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# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_26M) && defined(CONFIG_SPIRAM_SPEED_40M)
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movi a3, 4
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# else
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movi a3, 5
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# endif
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#elif defined(CONFIG_FLASHMODE_DIO) || defined(CONFIG_FLASHMODE_DOUT)
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# if defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_80M)
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movi a3, 3
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# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_40M)
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movi a3, 3
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# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_40M) && defined(CONFIG_SPIRAM_SPEED_40M)
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movi a3, 5
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# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_26M) && defined(CONFIG_SPIRAM_SPEED_40M)
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movi a3, 7
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# else
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movi a3, 9
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# endif
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#endif
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mull a3, a3, a4
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2: rsr.ccount a4 /* delay_us(N) */
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sub a4, a4, a2
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bltu a4, a3, 2b
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beqz a5, 2f
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movi a2, _l5_intr_livelock_app
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l32i a2, a2, 0
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beqi a2, 2, 8f
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j 3f
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2: movi a2, _l5_intr_livelock_pro
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l32i a4, a2, 0
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addi a4, a4, 1
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s32i a4, a2, 0
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movi a2, _l5_intr_livelock_sync
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movi a3, 1
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addx4 a3, a3, a2
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l32i a2, a2, 0
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l32i a3, a3, 0
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and a2, a2, a3
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beqz a2, 5f
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j 1b
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5: bgei a4, 2, 4f
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j 1b
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/*
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Pro cpu (Core 0) jump bypass, continue waiting, App cpu (Core 1)
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can execute to here, unmap itself tg1 1st stage timeout interrupt
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then restore registers and exit highint5.
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*/
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3: intr_matrix_map DPORT_APP_MAC_INTR_MAP_REG, ETS_TG1_WDT_LEVEL_INTR_SOURCE, 16
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j 9f
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/*
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Here, App cpu (Core 1) has exited isr, Pro cpu (Core 0) help the
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App cpu map tg1 1st stage timeout interrupt clear tg1 interrupt.
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*/
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4: intr_matrix_map DPORT_APP_MAC_INTR_MAP_REG, ETS_TG1_WDT_LEVEL_INTR_SOURCE, ETS_T1_WDT_INUM
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1: movi a2, _l5_intr_livelock_sync
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movi a4, 1
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addx4 a3, a4, a2
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l32i a2, a2, 0
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l32i a3, a3, 0
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and a2, a2, a3
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beqz a2, 1b /* Wait for App cpu to enter highint5 again */
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wdt_clr_intr_status TIMERG1
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j 9f
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/* Feed watchdog */
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8: wdt_feed TIMERG1
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9: wsr a0, PS /* restore iterrupt level */
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movi a0, 0
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beqz a5, 1f
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movi a2, _l5_intr_livelock_app
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l32i a3, a2, 0
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bnei a3, 2, 1f
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s32i a0, a2, 0
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1: bnez a5, 2f
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movi a2, _l5_intr_livelock_pro
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s32i a0, a2, 0
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2: movi a2, _l5_intr_livelock_sync
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addx4 a2, a5, a2
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s32i a0, a2, 0
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/* Done. Restore registers and return. */
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movi a0, L5_INTR_STACK_SIZE
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mull a5, a5, a0
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movi a0, _l5_intr_stack
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add a0, a0, a5
|
|
l32i a2, a0, L5_INTR_A2_OFFSET
|
|
l32i a3, a0, L5_INTR_A3_OFFSET
|
|
l32i a4, a0, L5_INTR_A4_OFFSET
|
|
rsync /* ensure register restored */
|
|
|
|
rsr a5, depc
|
|
|
|
rsr a0, EXCSAVE_5 /* restore a0 */
|
|
rfi 5
|
|
|
|
#endif
|
|
|
|
|
|
#ifndef CONFIG_FREERTOS_UNICORE
|
|
|
|
.align 4
|
|
.handle_dport_access_int:
|
|
/* This section is for dport access register protection */
|
|
/* Allocate exception frame and save minimal context. */
|
|
/* Because the interrupt cause code has protection that only
|
|
allows one cpu to enter in the dport section of the L5
|
|
interrupt at one time, there's no need to have two
|
|
_l5_intr_stack for each cpu */
|
|
|
|
/* This int is edge-triggered and needs clearing. */
|
|
movi a0, (1<<ETS_DPORT_INUM)
|
|
wsr a0, INTCLEAR
|
|
|
|
/* Save A2, A3, A4 so we can use those registers */
|
|
movi a0, _l5_intr_stack
|
|
s32i a2, a0, L5_INTR_A2_OFFSET
|
|
s32i a3, a0, L5_INTR_A3_OFFSET
|
|
s32i a4, a0, L5_INTR_A4_OFFSET
|
|
|
|
/* handle dport interrupt */
|
|
/* get CORE_ID */
|
|
getcoreid a0
|
|
beqz a0, 2f
|
|
|
|
/* current cpu is 1 */
|
|
movi a0, DPORT_CPU_INTR_FROM_CPU_3_REG
|
|
movi a2, 0
|
|
s32i a2, a0, 0 /* clear intr */
|
|
movi a0, 0 /* other cpu id */
|
|
j 3f
|
|
2:
|
|
/* current cpu is 0 */
|
|
movi a0, DPORT_CPU_INTR_FROM_CPU_2_REG
|
|
movi a2, 0
|
|
s32i a2, a0, 0 /* clear intr */
|
|
movi a0, 1 /* other cpu id */
|
|
3:
|
|
rsil a4, CONFIG_ESP32_DPORT_DIS_INTERRUPT_LVL /* disable nested iterrupt */
|
|
/* set and wait flag */
|
|
movi a2, dport_access_start
|
|
addx4 a2, a0, a2
|
|
movi a3, 1
|
|
s32i a3, a2, 0
|
|
memw
|
|
movi a2, dport_access_end
|
|
addx4 a2, a0, a2
|
|
.check_dport_access_end:
|
|
l32i a3, a2, 0
|
|
beqz a3, .check_dport_access_end
|
|
|
|
wsr a4, PS /* restore iterrupt level */
|
|
/* Done. Restore registers and return. */
|
|
movi a0, _l5_intr_stack
|
|
l32i a2, a0, L5_INTR_A2_OFFSET
|
|
l32i a3, a0, L5_INTR_A3_OFFSET
|
|
l32i a4, a0, L5_INTR_A4_OFFSET
|
|
rsync /* ensure register restored */
|
|
|
|
rsr a0, EXCSAVE_5 /* restore a0 */
|
|
rfi 5
|
|
|
|
#endif // CONFIG_FREERTOS_UNICORE
|
|
|
|
/* The linker has no reason to link in this file; all symbols it exports are already defined
|
|
(weakly!) in the default int handler. Define a symbol here so we can use it to have the
|
|
linker inspect this anyway. */
|
|
|
|
.global ld_include_panic_highint_hdl
|
|
ld_include_panic_highint_hdl:
|
|
|
|
|
|
|
|
|