mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
752 lines
37 KiB
C
752 lines
37 KiB
C
/**
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** TEE_HP2LP_TEE_PMS_DATE_REG register
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* NA
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*/
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#define TEE_HP2LP_TEE_PMS_DATE_REG (DR_REG_TEE_BASE + 0x0)
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/** TEE_TEE_DATE : R/W; bitpos: [31:0]; default: 2294790;
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* NA
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*/
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#define TEE_TEE_DATE 0xFFFFFFFFU
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#define TEE_TEE_DATE_M (TEE_TEE_DATE_V << TEE_TEE_DATE_S)
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#define TEE_TEE_DATE_V 0xFFFFFFFFU
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#define TEE_TEE_DATE_S 0
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/** TEE_PMS_CLK_EN_REG register
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* NA
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*/
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#define TEE_PMS_CLK_EN_REG (DR_REG_TEE_BASE + 0x4)
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/** TEE_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
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* NA
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*/
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#define TEE_REG_CLK_EN (BIT(0))
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#define TEE_REG_CLK_EN_M (TEE_REG_CLK_EN_V << TEE_REG_CLK_EN_S)
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#define TEE_REG_CLK_EN_V 0x00000001U
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#define TEE_REG_CLK_EN_S 0
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/** TEE_HP_CORE0_MM_PMS_REG0_REG register
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* NA
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*/
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#define TEE_HP_CORE0_MM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x8)
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/** TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
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* NA
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*/
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#define TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW (BIT(0))
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#define TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW_S)
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#define TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW_V 0x00000001U
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#define TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW_S 0
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/** TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
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* NA
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*/
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#define TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW (BIT(1))
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#define TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW_S)
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#define TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW_V 0x00000001U
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#define TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW_S 1
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/** TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
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* NA
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*/
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#define TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW (BIT(2))
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#define TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW_S)
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#define TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW_V 0x00000001U
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#define TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW_S 2
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/** TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
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* NA
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*/
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#define TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW (BIT(3))
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#define TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW_S)
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#define TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW_V 0x00000001U
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#define TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW_S 3
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/** TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
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* NA
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*/
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#define TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW (BIT(4))
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#define TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW_S)
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#define TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW_V 0x00000001U
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#define TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW_S 4
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/** TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
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* NA
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*/
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#define TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW (BIT(5))
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#define TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW_S)
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#define TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW_V 0x00000001U
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#define TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW_S 5
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/** TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
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* NA
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*/
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#define TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW (BIT(6))
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#define TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW_S)
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#define TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW_V 0x00000001U
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#define TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW_S 6
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/** TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
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* NA
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*/
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#define TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW (BIT(7))
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#define TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW_S)
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#define TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW_V 0x00000001U
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#define TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW_S 7
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/** TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
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* NA
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*/
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#define TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW (BIT(8))
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#define TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW_S)
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#define TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW_V 0x00000001U
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#define TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW_S 8
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/** TEE_REG_HP_CORE0_MM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
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* NA
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*/
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#define TEE_REG_HP_CORE0_MM_LP_UART_ALLOW (BIT(9))
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#define TEE_REG_HP_CORE0_MM_LP_UART_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_UART_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_UART_ALLOW_S)
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#define TEE_REG_HP_CORE0_MM_LP_UART_ALLOW_V 0x00000001U
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#define TEE_REG_HP_CORE0_MM_LP_UART_ALLOW_S 9
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/** TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
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* NA
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*/
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#define TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW (BIT(10))
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#define TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW_S)
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#define TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW_V 0x00000001U
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#define TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW_S 10
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/** TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
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* NA
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*/
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#define TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW (BIT(11))
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#define TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW_S)
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#define TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW_V 0x00000001U
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#define TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW_S 11
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/** TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
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* NA
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*/
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#define TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW (BIT(12))
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#define TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW_S)
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#define TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW_V 0x00000001U
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#define TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW_S 12
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/** TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
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* NA
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*/
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#define TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW (BIT(13))
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#define TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW_S)
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#define TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW_V 0x00000001U
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#define TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW_S 13
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/** TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
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* NA
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*/
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#define TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW (BIT(14))
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#define TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW_S)
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#define TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW_V 0x00000001U
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#define TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW_S 14
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/** TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
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* NA
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*/
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#define TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW (BIT(15))
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#define TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW_S)
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#define TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW_V 0x00000001U
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#define TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW_S 15
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/** TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
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* NA
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*/
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#define TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW (BIT(16))
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#define TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW_S)
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#define TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW_V 0x00000001U
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#define TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW_S 16
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/** TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
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* NA
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*/
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#define TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW (BIT(17))
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#define TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW_S)
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#define TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW_V 0x00000001U
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#define TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW_S 17
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/** TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
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* NA
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*/
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#define TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW (BIT(18))
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#define TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW_S)
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#define TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW_V 0x00000001U
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#define TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW_S 18
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/** TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
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* NA
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*/
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#define TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW (BIT(19))
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#define TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW_S)
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#define TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW_V 0x00000001U
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#define TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW_S 19
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/** TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
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* NA
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*/
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#define TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW (BIT(20))
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#define TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW_M (TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW_V << TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW_S)
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#define TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW_V 0x00000001U
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#define TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW_S 20
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/** TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
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* NA
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*/
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#define TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW (BIT(21))
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#define TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW_S)
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#define TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW_V 0x00000001U
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#define TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW_S 21
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/** TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
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* NA
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*/
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#define TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW (BIT(22))
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#define TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW_S)
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#define TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW_V 0x00000001U
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#define TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW_S 22
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/** TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW : R/W; bitpos: [23]; default: 1;
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* NA
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*/
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#define TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW (BIT(23))
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#define TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW_S)
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#define TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW_V 0x00000001U
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#define TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW_S 23
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/** TEE_HP_CORE0_UM_PMS_REG0_REG register
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* NA
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*/
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#define TEE_HP_CORE0_UM_PMS_REG0_REG (DR_REG_TEE_BASE + 0xc)
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/** TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
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* NA
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*/
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#define TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW (BIT(0))
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#define TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW_S)
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#define TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW_V 0x00000001U
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#define TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW_S 0
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/** TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
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* NA
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*/
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#define TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW (BIT(1))
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#define TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW_S)
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#define TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW_V 0x00000001U
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#define TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW_S 1
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/** TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
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* NA
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*/
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#define TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW (BIT(2))
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#define TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW_S)
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#define TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW_V 0x00000001U
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#define TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW_S 2
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/** TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
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* NA
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*/
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#define TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW (BIT(3))
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#define TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW_S)
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#define TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW_V 0x00000001U
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#define TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW_S 3
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/** TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
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* NA
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*/
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#define TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW (BIT(4))
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#define TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW_S)
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#define TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW_V 0x00000001U
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#define TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW_S 4
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/** TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
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* NA
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*/
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#define TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW (BIT(5))
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#define TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW_S)
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#define TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW_V 0x00000001U
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#define TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW_S 5
|
|
/** TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW (BIT(6))
|
|
#define TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW_S)
|
|
#define TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW_S 6
|
|
/** TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW (BIT(7))
|
|
#define TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW_S)
|
|
#define TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW_S 7
|
|
/** TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW (BIT(8))
|
|
#define TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW_S)
|
|
#define TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW_S 8
|
|
/** TEE_REG_HP_CORE0_UM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE0_UM_LP_UART_ALLOW (BIT(9))
|
|
#define TEE_REG_HP_CORE0_UM_LP_UART_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_UART_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_UART_ALLOW_S)
|
|
#define TEE_REG_HP_CORE0_UM_LP_UART_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE0_UM_LP_UART_ALLOW_S 9
|
|
/** TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW (BIT(10))
|
|
#define TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW_S)
|
|
#define TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW_S 10
|
|
/** TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW (BIT(11))
|
|
#define TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW_S)
|
|
#define TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW_S 11
|
|
/** TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW (BIT(12))
|
|
#define TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW_S)
|
|
#define TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW_S 12
|
|
/** TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW (BIT(13))
|
|
#define TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW_S)
|
|
#define TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW_S 13
|
|
/** TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW (BIT(14))
|
|
#define TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW_S)
|
|
#define TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW_S 14
|
|
/** TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW (BIT(15))
|
|
#define TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW_S)
|
|
#define TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW_S 15
|
|
/** TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW (BIT(16))
|
|
#define TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW_S)
|
|
#define TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW_S 16
|
|
/** TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW (BIT(17))
|
|
#define TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW_S)
|
|
#define TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW_S 17
|
|
/** TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW (BIT(18))
|
|
#define TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW_S)
|
|
#define TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW_S 18
|
|
/** TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW (BIT(19))
|
|
#define TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW_S)
|
|
#define TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW_S 19
|
|
/** TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW (BIT(20))
|
|
#define TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW_M (TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW_V << TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW_S)
|
|
#define TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW_S 20
|
|
/** TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW (BIT(21))
|
|
#define TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW_S)
|
|
#define TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW_S 21
|
|
/** TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW (BIT(22))
|
|
#define TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW_S)
|
|
#define TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW_S 22
|
|
/** TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW : R/W; bitpos: [23]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW (BIT(23))
|
|
#define TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW_S)
|
|
#define TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW_S 23
|
|
|
|
/** TEE_HP_CORE1_MM_PMS_REG0_REG register
|
|
* NA
|
|
*/
|
|
#define TEE_HP_CORE1_MM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x10)
|
|
/** TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW (BIT(0))
|
|
#define TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW_S 0
|
|
/** TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW (BIT(1))
|
|
#define TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW_S 1
|
|
/** TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW (BIT(2))
|
|
#define TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW_S 2
|
|
/** TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW (BIT(3))
|
|
#define TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW_S 3
|
|
/** TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW (BIT(4))
|
|
#define TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW_S 4
|
|
/** TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW (BIT(5))
|
|
#define TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW_S 5
|
|
/** TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW (BIT(6))
|
|
#define TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW_S 6
|
|
/** TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW (BIT(7))
|
|
#define TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW_S 7
|
|
/** TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW (BIT(8))
|
|
#define TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW_S 8
|
|
/** TEE_REG_HP_CORE1_MM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_MM_LP_UART_ALLOW (BIT(9))
|
|
#define TEE_REG_HP_CORE1_MM_LP_UART_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_UART_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_UART_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_MM_LP_UART_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_MM_LP_UART_ALLOW_S 9
|
|
/** TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW (BIT(10))
|
|
#define TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW_S 10
|
|
/** TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW (BIT(11))
|
|
#define TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW_S 11
|
|
/** TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW (BIT(12))
|
|
#define TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW_S 12
|
|
/** TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW (BIT(13))
|
|
#define TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW_S 13
|
|
/** TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW (BIT(14))
|
|
#define TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW_S 14
|
|
/** TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW (BIT(15))
|
|
#define TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW_S 15
|
|
/** TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW (BIT(16))
|
|
#define TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW_S 16
|
|
/** TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW (BIT(17))
|
|
#define TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW_S 17
|
|
/** TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW (BIT(18))
|
|
#define TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW_S 18
|
|
/** TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW (BIT(19))
|
|
#define TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW_S 19
|
|
/** TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW (BIT(20))
|
|
#define TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW_M (TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW_V << TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW_S 20
|
|
/** TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW (BIT(21))
|
|
#define TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW_S 21
|
|
/** TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW (BIT(22))
|
|
#define TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW_S 22
|
|
/** TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW : R/W; bitpos: [23]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW (BIT(23))
|
|
#define TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW_S 23
|
|
|
|
/** TEE_HP_CORE1_UM_PMS_REG0_REG register
|
|
* NA
|
|
*/
|
|
#define TEE_HP_CORE1_UM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x14)
|
|
/** TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW (BIT(0))
|
|
#define TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW_S 0
|
|
/** TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW (BIT(1))
|
|
#define TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW_S 1
|
|
/** TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW (BIT(2))
|
|
#define TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW_S 2
|
|
/** TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW (BIT(3))
|
|
#define TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW_S 3
|
|
/** TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW (BIT(4))
|
|
#define TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW_S 4
|
|
/** TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW (BIT(5))
|
|
#define TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW_S 5
|
|
/** TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW (BIT(6))
|
|
#define TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW_S 6
|
|
/** TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW (BIT(7))
|
|
#define TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW_S 7
|
|
/** TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW (BIT(8))
|
|
#define TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW_S 8
|
|
/** TEE_REG_HP_CORE1_UM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_UM_LP_UART_ALLOW (BIT(9))
|
|
#define TEE_REG_HP_CORE1_UM_LP_UART_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_UART_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_UART_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_UM_LP_UART_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_UM_LP_UART_ALLOW_S 9
|
|
/** TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW (BIT(10))
|
|
#define TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW_S 10
|
|
/** TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW (BIT(11))
|
|
#define TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW_S 11
|
|
/** TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW (BIT(12))
|
|
#define TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW_S 12
|
|
/** TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW (BIT(13))
|
|
#define TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW_S 13
|
|
/** TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW (BIT(14))
|
|
#define TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW_S 14
|
|
/** TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW (BIT(15))
|
|
#define TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW_S 15
|
|
/** TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW (BIT(16))
|
|
#define TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW_S 16
|
|
/** TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW (BIT(17))
|
|
#define TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW_S 17
|
|
/** TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW (BIT(18))
|
|
#define TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW_S 18
|
|
/** TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW (BIT(19))
|
|
#define TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW_S 19
|
|
/** TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW (BIT(20))
|
|
#define TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW_M (TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW_V << TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW_S 20
|
|
/** TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW (BIT(21))
|
|
#define TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW_S 21
|
|
/** TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW (BIT(22))
|
|
#define TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW_S 22
|
|
/** TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW : R/W; bitpos: [23]; default: 1;
|
|
* NA
|
|
*/
|
|
#define TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW (BIT(23))
|
|
#define TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW_S)
|
|
#define TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW_V 0x00000001U
|
|
#define TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW_S 23
|
|
|
|
/** TEE_REGDMA_PERI_PMS_REG register
|
|
* NA
|
|
*/
|
|
#define TEE_REGDMA_PERI_PMS_REG (DR_REG_TEE_BASE + 0x18)
|
|
/** TEE_REG_REGDMA_PERI_LP_RAM_ALLOW : R/W; bitpos: [0]; default: 1;
|
|
* NA
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*/
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#define TEE_REG_REGDMA_PERI_LP_RAM_ALLOW (BIT(0))
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#define TEE_REG_REGDMA_PERI_LP_RAM_ALLOW_M (TEE_REG_REGDMA_PERI_LP_RAM_ALLOW_V << TEE_REG_REGDMA_PERI_LP_RAM_ALLOW_S)
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#define TEE_REG_REGDMA_PERI_LP_RAM_ALLOW_V 0x00000001U
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#define TEE_REG_REGDMA_PERI_LP_RAM_ALLOW_S 0
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/** TEE_REG_REGDMA_PERI_LP_PERI_ALLOW : R/W; bitpos: [1]; default: 1;
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* NA
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*/
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#define TEE_REG_REGDMA_PERI_LP_PERI_ALLOW (BIT(1))
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#define TEE_REG_REGDMA_PERI_LP_PERI_ALLOW_M (TEE_REG_REGDMA_PERI_LP_PERI_ALLOW_V << TEE_REG_REGDMA_PERI_LP_PERI_ALLOW_S)
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#define TEE_REG_REGDMA_PERI_LP_PERI_ALLOW_V 0x00000001U
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#define TEE_REG_REGDMA_PERI_LP_PERI_ALLOW_S 1
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#ifdef __cplusplus
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}
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#endif
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