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https://github.com/espressif/esp-idf.git
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121 lines
6.6 KiB
C
121 lines
6.6 KiB
C
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef enum {
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PERIPH_LEDC_MODULE = 0,
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PERIPH_UART0_MODULE,
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PERIPH_UART1_MODULE,
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PERIPH_USB_DEVICE_MODULE,
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PERIPH_I2C0_MODULE,
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PERIPH_I2S1_MODULE,
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PERIPH_TIMG0_MODULE,
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PERIPH_TIMG1_MODULE,
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PERIPH_UHCI0_MODULE,
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PERIPH_RMT_MODULE,
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PERIPH_SPI_MODULE, //SPI1
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PERIPH_SPI2_MODULE, //SPI2
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PERIPH_TWAI_MODULE,
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PERIPH_RNG_MODULE,
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PERIPH_WIFI_MODULE,
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PERIPH_BT_MODULE,
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PERIPH_WIFI_BT_COMMON_MODULE,
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PERIPH_BT_BASEBAND_MODULE,
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PERIPH_BT_LC_MODULE,
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PERIPH_RSA_MODULE,
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PERIPH_AES_MODULE,
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PERIPH_SHA_MODULE,
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PERIPH_HMAC_MODULE,
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PERIPH_DS_MODULE,
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PERIPH_GDMA_MODULE,
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PERIPH_SYSTIMER_MODULE,
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PERIPH_SARADC_MODULE,
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PERIPH_MODULE_MAX
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} periph_module_t;
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typedef enum {
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ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/
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ETS_WIFI_MAC_NMI_SOURCE, /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/
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ETS_WIFI_PWR_INTR_SOURCE, /**< */
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ETS_WIFI_BB_INTR_SOURCE, /**< interrupt of WiFi BB, level, we can do some calibartion*/
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ETS_BT_MAC_INTR_SOURCE, /**< will be cancelled*/
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ETS_BT_BB_INTR_SOURCE, /**< interrupt of BT BB, level*/
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ETS_BT_BB_NMI_SOURCE, /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/
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ETS_RWBT_INTR_SOURCE, /**< interrupt of RWBT, level*/
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ETS_RWBLE_INTR_SOURCE, /**< interrupt of RWBLE, level*/
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ETS_RWBT_NMI_SOURCE, /**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/
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ETS_RWBLE_NMI_SOURCE, /**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/
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ETS_I2C_MASTER_SOURCE, /**< interrupt of I2C Master, level*/
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ETS_SLC0_INTR_SOURCE, /**< interrupt of SLC0, level*/
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ETS_SLC1_INTR_SOURCE, /**< interrupt of SLC1, level*/
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ETS_APB_CTRL_INTR_SOURCE, /**< interrupt of APB ctrl, ?*/
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ETS_UHCI0_INTR_SOURCE, /**< interrupt of UHCI0, level*/
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ETS_GPIO_INTR_SOURCE, /**< interrupt of GPIO, level*/
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ETS_GPIO_NMI_SOURCE, /**< interrupt of GPIO, NMI*/
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ETS_SPI1_INTR_SOURCE, /**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/
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ETS_SPI2_INTR_SOURCE, /**< interrupt of SPI2, level*/
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ETS_I2S1_INTR_SOURCE, /**< interrupt of I2S1, level*/
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ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/
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ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/
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ETS_LEDC_INTR_SOURCE, /**< interrupt of LED PWM, level*/
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ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/
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ETS_TWAI_INTR_SOURCE, /**< interrupt of can, level*/
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ETS_USB_INTR_SOURCE, /**< interrupt of USB, level*/
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ETS_RTC_CORE_INTR_SOURCE, /**< interrupt of rtc core, level, include rtc watchdog*/
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ETS_RMT_INTR_SOURCE, /**< interrupt of remote controller, level*/
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ETS_I2C_EXT0_INTR_SOURCE, /**< interrupt of I2C controller1, level*/
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ETS_TIMER1_INTR_SOURCE,
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ETS_TIMER2_INTR_SOURCE,
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ETS_TG0_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, level*/
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ETS_TG0_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCH DOG, level*/
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ETS_TG1_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, level*/
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ETS_TG1_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/
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ETS_CACHE_IA_INTR_SOURCE, /**< interrupt of Cache Invalied Access, LEVEL*/
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ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE, /**< interrupt of system timer 0, EDGE*/
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ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE, /**< interrupt of system timer 1, EDGE*/
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ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, /**< interrupt of system timer 2, EDGE*/
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ETS_SPI_MEM_REJECT_CACHE_INTR_SOURCE, /**< interrupt of SPI0 Cache access and SPI1 access rejected, LEVEL*/
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ETS_ICACHE_PRELOAD0_INTR_SOURCE, /**< interrupt of ICache perload operation, LEVEL*/
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ETS_ICACHE_SYNC0_INTR_SOURCE, /**< interrupt of instruction cache sync done, LEVEL*/
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ETS_APB_ADC_INTR_SOURCE, /**< interrupt of APB ADC, LEVEL*/
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ETS_DMA_CH0_INTR_SOURCE, /**< interrupt of general DMA channel 0, LEVEL*/
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ETS_DMA_CH1_INTR_SOURCE, /**< interrupt of general DMA channel 1, LEVEL*/
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ETS_DMA_CH2_INTR_SOURCE, /**< interrupt of general DMA channel 2, LEVEL*/
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ETS_RSA_INTR_SOURCE, /**< interrupt of RSA accelerator, level*/
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ETS_AES_INTR_SOURCE, /**< interrupt of AES accelerator, level*/
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ETS_SHA_INTR_SOURCE, /**< interrupt of SHA accelerator, level*/
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ETS_FROM_CPU_INTR0_SOURCE, /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */
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ETS_FROM_CPU_INTR1_SOURCE, /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */
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ETS_FROM_CPU_INTR2_SOURCE, /**< interrupt2 generated from a CPU, level*/ /* Used for DPORT Access */
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ETS_FROM_CPU_INTR3_SOURCE, /**< interrupt3 generated from a CPU, level*/ /* Used for DPORT Access */
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ETS_ASSIST_DEBUG_INTR_SOURCE, /**< interrupt of Assist debug module, LEVEL*/
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ETS_DMA_APBPERI_PMS_INTR_SOURCE,
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ETS_CORE0_IRAM0_PMS_INTR_SOURCE,
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ETS_CORE0_DRAM0_PMS_INTR_SOURCE,
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ETS_CORE0_PIF_PMS_INTR_SOURCE,
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ETS_CORE0_PIF_PMS_SIZE_INTR_SOURCE,
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ETS_BAK_PMS_VIOLATE_INTR_SOURCE,
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ETS_CACHE_CORE0_ACS_INTR_SOURCE,
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ETS_MAX_INTR_SOURCE,
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} periph_interrput_t;
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#ifdef __cplusplus
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}
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#endif
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