mirror of
https://github.com/espressif/esp-idf.git
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653d8b5bdd
1. remove speed dependency of SPIRAM 2. support wrap mode of cache, flash and SPIRAM 3. fix some bugs on cache modes support
609 lines
22 KiB
C
609 lines
22 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdlib.h>
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#include <assert.h>
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#include <string.h>
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#include <stdio.h>
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#include <freertos/FreeRTOS.h>
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#include <freertos/task.h>
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#include <freertos/semphr.h>
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#if CONFIG_IDF_TARGET_ESP32
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#include <esp32/rom/spi_flash.h>
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#include <esp32/rom/cache.h>
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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#include "esp32s2beta/rom/spi_flash.h"
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#include "esp32s2beta/rom/cache.h"
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#endif
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#include <soc/soc.h>
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#include <soc/dport_reg.h>
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#include "sdkconfig.h"
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#include "esp_ipc.h"
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#include "esp_attr.h"
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#include "esp_intr_alloc.h"
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#include "esp_spi_flash.h"
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#include "esp_log.h"
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static __attribute__((unused)) const char* TAG = "spiflash";
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static void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t* saved_state);
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static void IRAM_ATTR spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_state);
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static uint32_t s_flash_op_cache_state[2];
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#ifndef CONFIG_FREERTOS_UNICORE
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static SemaphoreHandle_t s_flash_op_mutex;
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static volatile bool s_flash_op_can_start = false;
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static volatile bool s_flash_op_complete = false;
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#ifndef NDEBUG
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static volatile int s_flash_op_cpu = -1;
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#endif
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void spi_flash_init_lock(void)
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{
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s_flash_op_mutex = xSemaphoreCreateRecursiveMutex();
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assert(s_flash_op_mutex != NULL);
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}
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void spi_flash_op_lock(void)
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{
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xSemaphoreTakeRecursive(s_flash_op_mutex, portMAX_DELAY);
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}
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void spi_flash_op_unlock(void)
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{
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xSemaphoreGiveRecursive(s_flash_op_mutex);
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}
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/*
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If you're going to modify this, keep in mind that while the flash caches of the pro and app
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cpu are separate, the psram cache is *not*. If one of the CPUs returns from a flash routine
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with its cache enabled but the other CPUs cache is not enabled yet, you will have problems
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when accessing psram from the former CPU.
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*/
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void IRAM_ATTR spi_flash_op_block_func(void* arg)
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{
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// Disable scheduler on this CPU
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vTaskSuspendAll();
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// Restore interrupts that aren't located in IRAM
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esp_intr_noniram_disable();
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uint32_t cpuid = (uint32_t) arg;
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// s_flash_op_complete flag is cleared on *this* CPU, otherwise the other
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// CPU may reset the flag back to false before IPC task has a chance to check it
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// (if it is preempted by an ISR taking non-trivial amount of time)
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s_flash_op_complete = false;
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s_flash_op_can_start = true;
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while (!s_flash_op_complete) {
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// busy loop here and wait for the other CPU to finish flash operation
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}
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// Flash operation is complete, re-enable cache
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spi_flash_restore_cache(cpuid, s_flash_op_cache_state[cpuid]);
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// Restore interrupts that aren't located in IRAM
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esp_intr_noniram_enable();
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// Re-enable scheduler
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xTaskResumeAll();
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}
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void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu(void)
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{
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spi_flash_op_lock();
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const uint32_t cpuid = xPortGetCoreID();
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const uint32_t other_cpuid = (cpuid == 0) ? 1 : 0;
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#ifndef NDEBUG
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// For sanity check later: record the CPU which has started doing flash operation
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assert(s_flash_op_cpu == -1);
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s_flash_op_cpu = cpuid;
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#endif
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if (xTaskGetSchedulerState() == taskSCHEDULER_NOT_STARTED) {
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// Scheduler hasn't been started yet, it means that spi_flash API is being
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// called from the 2nd stage bootloader or from user_start_cpu0, i.e. from
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// PRO CPU. APP CPU is either in reset or spinning inside user_start_cpu1,
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// which is in IRAM. So it is safe to disable cache for the other_cpuid here.
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assert(other_cpuid == 1);
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spi_flash_disable_cache(other_cpuid, &s_flash_op_cache_state[other_cpuid]);
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} else {
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// Temporarily raise current task priority to prevent a deadlock while
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// waiting for IPC task to start on the other CPU
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int old_prio = uxTaskPriorityGet(NULL);
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vTaskPrioritySet(NULL, configMAX_PRIORITIES - 1);
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// Signal to the spi_flash_op_block_task on the other CPU that we need it to
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// disable cache there and block other tasks from executing.
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s_flash_op_can_start = false;
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esp_err_t ret = esp_ipc_call(other_cpuid, &spi_flash_op_block_func, (void*) other_cpuid);
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assert(ret == ESP_OK);
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while (!s_flash_op_can_start) {
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// Busy loop and wait for spi_flash_op_block_func to disable cache
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// on the other CPU
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}
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// Disable scheduler on the current CPU
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vTaskSuspendAll();
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// Can now set the priority back to the normal one
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vTaskPrioritySet(NULL, old_prio);
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// This is guaranteed to run on CPU <cpuid> because the other CPU is now
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// occupied by highest priority task
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assert(xPortGetCoreID() == cpuid);
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}
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// Kill interrupts that aren't located in IRAM
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esp_intr_noniram_disable();
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// This CPU executes this routine, with non-IRAM interrupts and the scheduler
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// disabled. The other CPU is spinning in the spi_flash_op_block_func task, also
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// with non-iram interrupts and the scheduler disabled. None of these CPUs will
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// touch external RAM or flash this way, so we can safely disable caches.
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spi_flash_disable_cache(cpuid, &s_flash_op_cache_state[cpuid]);
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spi_flash_disable_cache(other_cpuid, &s_flash_op_cache_state[other_cpuid]);
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}
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void IRAM_ATTR spi_flash_enable_interrupts_caches_and_other_cpu(void)
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{
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const uint32_t cpuid = xPortGetCoreID();
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const uint32_t other_cpuid = (cpuid == 0) ? 1 : 0;
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#ifndef NDEBUG
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// Sanity check: flash operation ends on the same CPU as it has started
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assert(cpuid == s_flash_op_cpu);
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// More sanity check: if scheduler isn't started, only CPU0 can call this.
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assert(!(xTaskGetSchedulerState() == taskSCHEDULER_NOT_STARTED && cpuid != 0));
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s_flash_op_cpu = -1;
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#endif
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// Re-enable cache on both CPUs. After this, cache (flash and external RAM) should work again.
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spi_flash_restore_cache(cpuid, s_flash_op_cache_state[cpuid]);
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spi_flash_restore_cache(other_cpuid, s_flash_op_cache_state[other_cpuid]);
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if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) {
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// Signal to spi_flash_op_block_task that flash operation is complete
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s_flash_op_complete = true;
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}
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// Re-enable non-iram interrupts
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esp_intr_noniram_enable();
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// Resume tasks on the current CPU, if the scheduler has started.
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// NOTE: enabling non-IRAM interrupts has to happen before this,
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// because once the scheduler has started, due to preemption the
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// current task can end up being moved to the other CPU.
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// But esp_intr_noniram_enable has to be called on the same CPU which
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// called esp_intr_noniram_disable
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if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) {
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xTaskResumeAll();
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}
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// Release API lock
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spi_flash_op_unlock();
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}
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void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu_no_os(void)
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{
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const uint32_t cpuid = xPortGetCoreID();
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const uint32_t other_cpuid = (cpuid == 0) ? 1 : 0;
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// do not care about other CPU, it was halted upon entering panic handler
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spi_flash_disable_cache(other_cpuid, &s_flash_op_cache_state[other_cpuid]);
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// Kill interrupts that aren't located in IRAM
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esp_intr_noniram_disable();
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// Disable cache on this CPU as well
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spi_flash_disable_cache(cpuid, &s_flash_op_cache_state[cpuid]);
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}
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void IRAM_ATTR spi_flash_enable_interrupts_caches_no_os(void)
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{
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const uint32_t cpuid = xPortGetCoreID();
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// Re-enable cache on this CPU
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spi_flash_restore_cache(cpuid, s_flash_op_cache_state[cpuid]);
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// Re-enable non-iram interrupts
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esp_intr_noniram_enable();
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}
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#else // CONFIG_FREERTOS_UNICORE
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void spi_flash_init_lock(void)
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{
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}
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void spi_flash_op_lock(void)
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{
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vTaskSuspendAll();
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}
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void spi_flash_op_unlock(void)
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{
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xTaskResumeAll();
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}
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void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu(void)
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{
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spi_flash_op_lock();
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esp_intr_noniram_disable();
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spi_flash_disable_cache(0, &s_flash_op_cache_state[0]);
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}
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void IRAM_ATTR spi_flash_enable_interrupts_caches_and_other_cpu(void)
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{
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spi_flash_restore_cache(0, s_flash_op_cache_state[0]);
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esp_intr_noniram_enable();
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spi_flash_op_unlock();
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}
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void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu_no_os(void)
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{
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// Kill interrupts that aren't located in IRAM
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esp_intr_noniram_disable();
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// Disable cache on this CPU as well
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spi_flash_disable_cache(0, &s_flash_op_cache_state[0]);
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}
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void IRAM_ATTR spi_flash_enable_interrupts_caches_no_os(void)
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{
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// Re-enable cache on this CPU
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spi_flash_restore_cache(0, s_flash_op_cache_state[0]);
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// Re-enable non-iram interrupts
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esp_intr_noniram_enable();
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}
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#endif // CONFIG_FREERTOS_UNICORE
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/**
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* The following two functions are replacements for Cache_Read_Disable and Cache_Read_Enable
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* function in ROM. They are used to work around a bug where Cache_Read_Disable requires a call to
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* Cache_Flush before Cache_Read_Enable, even if cached data was not modified.
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*/
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#if CONFIG_IDF_TARGET_ESP32
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static const uint32_t cache_mask = DPORT_APP_CACHE_MASK_OPSDRAM | DPORT_APP_CACHE_MASK_DROM0 |
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DPORT_APP_CACHE_MASK_DRAM1 | DPORT_APP_CACHE_MASK_IROM0 |
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DPORT_APP_CACHE_MASK_IRAM1 | DPORT_APP_CACHE_MASK_IRAM0;
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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// static const uint32_t icache_mask = DPORT_PRO_ICACHE_MASK_DROM0 |DPORT_PRO_ICACHE_MASK_IROM0 |
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// DPORT_PRO_ICACHE_MASK_IRAM1 | DPORT_PRO_ICACHE_MASK_IRAM0;
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// static const uint32_t dcache_mask = DPORT_PRO_DCACHE_MASK_DRAM1 | DPORT_PRO_DCACHE_MASK_DRAM0 |
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// DPORT_PRO_DCACHE_MASK_DPORT | DPORT_PRO_DCACHE_MASK_DROM0;
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#endif
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static void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t* saved_state)
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{
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#if CONFIG_IDF_TARGET_ESP32
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uint32_t ret = 0;
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if (cpuid == 0) {
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ret |= DPORT_GET_PERI_REG_BITS2(DPORT_PRO_CACHE_CTRL1_REG, cache_mask, 0);
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while (DPORT_GET_PERI_REG_BITS2(DPORT_PRO_DCACHE_DBUG0_REG, DPORT_PRO_CACHE_STATE, DPORT_PRO_CACHE_STATE_S) != 1) {
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;
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}
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DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 0, DPORT_PRO_CACHE_ENABLE_S);
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}
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#if !CONFIG_FREERTOS_UNICORE
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else {
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ret |= DPORT_GET_PERI_REG_BITS2(DPORT_APP_CACHE_CTRL1_REG, cache_mask, 0);
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while (DPORT_GET_PERI_REG_BITS2(DPORT_APP_DCACHE_DBUG0_REG, DPORT_APP_CACHE_STATE, DPORT_APP_CACHE_STATE_S) != 1) {
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;
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}
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DPORT_SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 0, DPORT_APP_CACHE_ENABLE_S);
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}
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#endif
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*saved_state = ret;
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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*saved_state = Cache_Suspend_ICache();
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if (!Cache_Drom0_Using_ICache()) {
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*(saved_state + 1) = Cache_Suspend_DCache();
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}
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#endif
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}
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static void IRAM_ATTR spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_state)
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{
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#if CONFIG_IDF_TARGET_ESP32
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if (cpuid == 0) {
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DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 1, DPORT_PRO_CACHE_ENABLE_S);
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DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL1_REG, cache_mask, saved_state, 0);
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}
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#if !CONFIG_FREERTOS_UNICORE
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else {
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DPORT_SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 1, DPORT_APP_CACHE_ENABLE_S);
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DPORT_SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL1_REG, cache_mask, saved_state, 0);
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}
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#endif
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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Cache_Resume_ICache(saved_state);
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if (!Cache_Drom0_Using_ICache()) {
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Cache_Resume_DCache(s_flash_op_cache_state[1]);
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}
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#endif
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}
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IRAM_ATTR bool spi_flash_cache_enabled(void)
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{
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#if CONFIG_IDF_TARGET_ESP32
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bool result = (DPORT_REG_GET_BIT(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_CACHE_ENABLE) != 0);
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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bool result = (DPORT_REG_GET_BIT(DPORT_PRO_ICACHE_CTRL_REG, DPORT_PRO_ICACHE_ENABLE) != 0);
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if (!Cache_Drom0_Using_ICache()) {
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result = result && (DPORT_REG_GET_BIT(DPORT_PRO_DCACHE_CTRL_REG, DPORT_PRO_DCACHE_ENABLE) != 0);
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}
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#endif
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#if portNUM_PROCESSORS == 2
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result = result && (DPORT_REG_GET_BIT(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_CACHE_ENABLE) != 0);
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#endif
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return result;
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}
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#if CONFIG_IDF_TARGET_ESP32S2BETA
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IRAM_ATTR void esp_config_instruction_cache_mode(void)
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{
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cache_size_t cache_size;
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cache_ways_t cache_ways;
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cache_line_size_t cache_line_size;
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#if CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB
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Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);
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cache_size = CACHE_SIZE_8KB;
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#else
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Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH, CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);
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cache_size = CACHE_SIZE_16KB;
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#endif
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#if CONFIG_ESP32S2_INSTRUCTION_CACHE_4WAYS
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cache_ways = CACHE_4WAYS_ASSOC;
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#else
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cache_ways = CACHE_8WAYS_ASSOC;
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#endif
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#if CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_16B
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cache_line_size = CACHE_LINE_SIZE_16B;
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#elif CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_32B
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cache_line_size = CACHE_LINE_SIZE_32B;
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#else
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cache_line_size = CACHE_LINE_SIZE_64B;
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#endif
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ESP_EARLY_LOGI(TAG, "Instruction cache \t: size %dKB, %dWays, cache line size %dByte", cache_size == CACHE_SIZE_8KB ? 8 : 16,cache_ways == CACHE_4WAYS_ASSOC ? 4: 8, cache_line_size == CACHE_LINE_SIZE_16B ? 16 : (cache_line_size == CACHE_LINE_SIZE_32B ? 32 : 64));
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Cache_Suspend_ICache();
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Cache_Set_ICache_Mode(cache_size, cache_ways, cache_line_size);
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Cache_Invalidate_ICache_All();
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Cache_Resume_ICache(0);
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}
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IRAM_ATTR void esp_config_data_cache_mode(void)
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{
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cache_size_t cache_size;
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cache_ways_t cache_ways;
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cache_line_size_t cache_line_size;
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#if CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB
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#if CONFIG_ESP32S2_DATA_CACHE_8KB
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Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_DCACHE_LOW, CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);
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cache_size = CACHE_SIZE_8KB;
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#else
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Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_DCACHE_LOW, CACHE_MEMORY_DCACHE_HIGH, CACHE_MEMORY_INVALID);
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cache_size = CACHE_SIZE_16KB;
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#endif
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#else
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#if CONFIG_ESP32S2_DATA_CACHE_8KB
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Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH, CACHE_MEMORY_DCACHE_LOW, CACHE_MEMORY_INVALID);
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cache_size = CACHE_SIZE_8KB;
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#else
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Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH, CACHE_MEMORY_DCACHE_LOW, CACHE_MEMORY_DCACHE_HIGH);
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cache_size = CACHE_SIZE_16KB;
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#endif
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#endif
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#if CONFIG_ESP32S2_DATA_CACHE_4WAYS
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cache_ways = CACHE_4WAYS_ASSOC;
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#else
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cache_ways = CACHE_8WAYS_ASSOC;
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#endif
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#if CONFIG_ESP32S2_DATA_CACHE_LINE_16B
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cache_line_size = CACHE_LINE_SIZE_16B;
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#elif CONFIG_ESP32S2_DATA_CACHE_LINE_32B
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cache_line_size = CACHE_LINE_SIZE_32B;
|
|
#else
|
|
cache_line_size = CACHE_LINE_SIZE_64B;
|
|
#endif
|
|
ESP_EARLY_LOGI(TAG, "Data cache \t\t: size %dKB, %dWays, cache line size %dByte", cache_size == CACHE_SIZE_8KB ? 8 : 16, cache_ways == CACHE_4WAYS_ASSOC ? 4: 8, cache_line_size == CACHE_LINE_SIZE_16B ? 16 : (cache_line_size == CACHE_LINE_SIZE_32B ? 32 : 64));
|
|
Cache_Set_DCache_Mode(cache_size, cache_ways, cache_line_size);
|
|
Cache_Invalidate_DCache_All();
|
|
}
|
|
|
|
void esp_switch_rodata_to_dcache(void)
|
|
{
|
|
REG_CLR_BIT(DPORT_PRO_DCACHE_CTRL1_REG, DPORT_PRO_DCACHE_MASK_DROM0);
|
|
Cache_Drom0_Source_DCache();
|
|
MMU_Drom_ICache_Unmap();
|
|
REG_SET_BIT(DPORT_PRO_ICACHE_CTRL1_REG, DPORT_PRO_ICACHE_MASK_DROM0);
|
|
ESP_EARLY_LOGI(TAG, "Switch rodata load path to data cache.");
|
|
}
|
|
|
|
static IRAM_ATTR void esp_enable_cache_flash_wrap(bool icache, bool dcache)
|
|
{
|
|
uint32_t i_autoload, d_autoload;
|
|
if (icache) {
|
|
i_autoload = Cache_Suspend_ICache();
|
|
}
|
|
if (dcache) {
|
|
d_autoload = Cache_Suspend_DCache();
|
|
}
|
|
REG_SET_BIT(DPORT_PRO_CACHE_WRAP_AROUND_CTRL_REG, DPORT_PRO_CACHE_FLASH_WRAP_AROUND);
|
|
if (icache) {
|
|
Cache_Resume_ICache(i_autoload);
|
|
}
|
|
if (dcache) {
|
|
Cache_Resume_DCache(d_autoload);
|
|
}
|
|
}
|
|
|
|
#if CONFIG_ESP32S2_SPIRAM_SUPPORT
|
|
static IRAM_ATTR void esp_enable_cache_spiram_wrap(bool icache, bool dcache)
|
|
{
|
|
uint32_t i_autoload, d_autoload;
|
|
if (icache) {
|
|
i_autoload = Cache_Suspend_ICache();
|
|
}
|
|
if (dcache) {
|
|
d_autoload = Cache_Suspend_DCache();
|
|
}
|
|
REG_SET_BIT(DPORT_PRO_CACHE_WRAP_AROUND_CTRL_REG, DPORT_PRO_CACHE_SRAM_RD_WRAP_AROUND);
|
|
if (icache) {
|
|
Cache_Resume_ICache(i_autoload);
|
|
}
|
|
if (dcache) {
|
|
Cache_Resume_DCache(d_autoload);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable)
|
|
{
|
|
int icache_wrap_size = 0, dcache_wrap_size = 0;
|
|
int flash_wrap_sizes[2]={-1, -1}, spiram_wrap_sizes[2]={-1, -1};
|
|
int flash_wrap_size = 0, spiram_wrap_size = 0;
|
|
int flash_count = 0, spiram_count = 0;
|
|
int i;
|
|
bool flash_spiram_wrap_together, flash_support_wrap = true, spiram_support_wrap = true;
|
|
if (icache_wrap_enable) {
|
|
#if CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_16B
|
|
icache_wrap_size = 16;
|
|
#elif CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_32B
|
|
icache_wrap_size = 32;
|
|
#else
|
|
icache_wrap_size = 64;
|
|
#endif
|
|
}
|
|
if (dcache_wrap_enable) {
|
|
#if CONFIG_ESP32S2_DATA_CACHE_LINE_16B
|
|
dcache_wrap_size = 16;
|
|
#elif CONFIG_ESP32S2_DATA_CACHE_LINE_32B
|
|
dcache_wrap_size = 32;
|
|
#else
|
|
dcache_wrap_size = 64;
|
|
#endif
|
|
}
|
|
|
|
uint32_t instruction_use_spiram = 0;
|
|
uint32_t rodata_use_spiram = 0;
|
|
#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS
|
|
extern uint32_t esp_spiram_instruction_access_enabled();
|
|
instruction_use_spiram = esp_spiram_instruction_access_enabled();
|
|
#endif
|
|
#if CONFIG_SPIRAM_RODATA
|
|
extern uint32_t esp_spiram_rodata_access_enabled();
|
|
rodata_use_spiram = esp_spiram_rodata_access_enabled();
|
|
#endif
|
|
|
|
if (instruction_use_spiram) {
|
|
spiram_wrap_sizes[0] = icache_wrap_size;
|
|
} else {
|
|
flash_wrap_sizes[0] = icache_wrap_size;
|
|
}
|
|
if (rodata_use_spiram) {
|
|
if (Cache_Drom0_Using_ICache()) {
|
|
spiram_wrap_sizes[0] = icache_wrap_size;
|
|
} else {
|
|
spiram_wrap_sizes[1] = dcache_wrap_size;
|
|
}
|
|
#ifdef CONFIG_EXT_RODATA_SUPPORT
|
|
spiram_wrap_sizes[1] = dcache_wrap_size;
|
|
#endif
|
|
} else {
|
|
if (Cache_Drom0_Using_ICache()) {
|
|
flash_wrap_sizes[0] = icache_wrap_size;
|
|
} else {
|
|
flash_wrap_sizes[1] = dcache_wrap_size;
|
|
}
|
|
#ifdef CONFIG_EXT_RODATA_SUPPORT
|
|
flash_wrap_sizes[1] = dcache_wrap_size;
|
|
#endif
|
|
}
|
|
#ifdef CONFIG_ESP32S2_SPIRAM_SUPPORT
|
|
spiram_wrap_sizes[1] = dcache_wrap_size;
|
|
#endif
|
|
for (i = 0; i < 2; i++) {
|
|
if (flash_wrap_sizes[i] != -1) {
|
|
flash_count++;
|
|
flash_wrap_size = flash_wrap_sizes[i];
|
|
}
|
|
}
|
|
for (i = 0; i < 2; i++) {
|
|
if (spiram_wrap_sizes[i] != -1) {
|
|
spiram_count++;
|
|
spiram_wrap_size = spiram_wrap_sizes[i];
|
|
}
|
|
}
|
|
if (flash_count + spiram_count <= 2) {
|
|
flash_spiram_wrap_together = false;
|
|
} else {
|
|
flash_spiram_wrap_together = true;
|
|
}
|
|
ESP_EARLY_LOGI(TAG, "flash_count=%d, size=%d, spiram_count=%d, size=%d,together=%d", flash_count, flash_wrap_size, spiram_count, spiram_wrap_size, flash_spiram_wrap_together);
|
|
if (flash_count > 1 && flash_wrap_sizes[0] != flash_wrap_sizes[1]) {
|
|
ESP_EARLY_LOGW(TAG, "Flash wrap with different length %d and %d, abort wrap.", flash_wrap_sizes[0], flash_wrap_sizes[1]);
|
|
if (spiram_wrap_size == 0) {
|
|
return ESP_FAIL;
|
|
}
|
|
if (flash_spiram_wrap_together) {
|
|
ESP_EARLY_LOGE(TAG, "Abort spiram wrap because flash wrap length not fixed.");
|
|
return ESP_FAIL;
|
|
}
|
|
}
|
|
if (spiram_count > 1 && spiram_wrap_sizes[0] != spiram_wrap_sizes[1]) {
|
|
ESP_EARLY_LOGW(TAG, "SPIRAM wrap with different length %d and %d, abort wrap.", spiram_wrap_sizes[0], spiram_wrap_sizes[1]);
|
|
if (flash_wrap_size == 0) {
|
|
return ESP_FAIL;
|
|
}
|
|
if (flash_spiram_wrap_together) {
|
|
ESP_EARLY_LOGW(TAG, "Abort flash wrap because spiram wrap length not fixed.");
|
|
return ESP_FAIL;
|
|
}
|
|
}
|
|
|
|
if (flash_spiram_wrap_together && flash_wrap_size != spiram_wrap_size) {
|
|
ESP_EARLY_LOGW(TAG, "SPIRAM has different wrap length with flash, %d and %d, abort wrap.", spiram_wrap_size, flash_wrap_size);
|
|
return ESP_FAIL;
|
|
}
|
|
|
|
extern bool spi_flash_support_wrap_size(uint32_t wrap_size);
|
|
if (!spi_flash_support_wrap_size(flash_wrap_size)) {
|
|
flash_support_wrap = false;
|
|
ESP_EARLY_LOGW(TAG, "Flash do not support wrap size %d.", flash_wrap_size);
|
|
}
|
|
|
|
#ifdef CONFIG_ESP32S2_SPIRAM_SUPPORT
|
|
extern bool psram_support_wrap_size(uint32_t wrap_size);
|
|
if (!psram_support_wrap_size(spiram_wrap_size)) {
|
|
spiram_support_wrap = false;
|
|
ESP_EARLY_LOGW(TAG, "SPIRAM do not support wrap size %d.", spiram_wrap_size);
|
|
}
|
|
#endif
|
|
|
|
if (flash_spiram_wrap_together && !(flash_support_wrap && spiram_support_wrap)) {
|
|
ESP_EARLY_LOGW(TAG, "Flash and SPIRAM should support wrap together.");
|
|
return ESP_FAIL;
|
|
}
|
|
|
|
extern esp_err_t spi_flash_enable_wrap(uint32_t wrap_size);
|
|
if (flash_support_wrap && flash_wrap_size > 0) {
|
|
ESP_EARLY_LOGI(TAG, "Flash wrap enabled.");
|
|
spi_flash_enable_wrap(flash_wrap_size);
|
|
esp_enable_cache_flash_wrap((flash_wrap_sizes[0] > 0), (flash_wrap_sizes[1] > 0));
|
|
}
|
|
#if CONFIG_ESP32S2_SPIRAM_SUPPORT
|
|
extern esp_err_t psram_enable_wrap(uint32_t wrap_size);
|
|
if (spiram_support_wrap && spiram_wrap_size > 0) {
|
|
ESP_EARLY_LOGI(TAG, "SPIRAM wrap enabled.");
|
|
psram_enable_wrap(spiram_wrap_size);
|
|
esp_enable_cache_spiram_wrap((spiram_wrap_sizes[0] > 0), (spiram_wrap_sizes[1] > 0));
|
|
}
|
|
#endif
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
#endif
|