Mahavir Jain 9ecd2fd7e3 fix(soc): change debug addr range to CPU subsystem range ... For C6/H2/P4/C5, there is no SoC specific debug range. Instead the same address range is part of CPU Subsystem range which contains debug mode specific code and interrupt config registers (CLINT, PLIC etc.). For now the PMP entry is provided with RWX permission for both machine and user mode but we can save this entry and allow the access to only machine mode for this range. For P4/C5 case, this PMP entry can have RW permission as the debug mode specific code is not present in this memory range.		2024-01-22 13:34:32 +08:00
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include	fix(soc): change debug addr range to CPU subsystem range	2024-01-22 13:34:32 +08:00
ld	change(esp32c5): update soc files for esp32c5 beta3	2023-12-28 10:23:15 +08:00
gpio_periph.c	feat(esp32c5): introduce target esp32c5	2023-11-28 16:14:17 +08:00
interrupts.c	change(esp32c5): update soc files for esp32c5 beta3	2023-12-28 10:23:15 +08:00
uart_periph.c	feat(esp32c5): introduce target esp32c5	2023-11-28 16:14:17 +08:00