mirror of
https://github.com/espressif/esp-idf.git
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baa7898e35
1. update register file about adc; 2. fix adc driver; 3. add UT for adc/dac; See merge request espressif/esp-idf!7776
494 lines
17 KiB
C
494 lines
17 KiB
C
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/*
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Tests for the adc device driver
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*/
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#include "esp_system.h"
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#include "driver/adc.h"
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#include "driver/dac.h"
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#include "driver/rtc_io.h"
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#include "driver/gpio.h"
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#include "unity.h"
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#include "esp_system.h"
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#include "esp_event.h"
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#include "esp_wifi.h"
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#include "esp_log.h"
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#include "nvs_flash.h"
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#include "test_utils.h"
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#include "soc/spi_reg.h"
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#include "soc/adc_periph.h"
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#if !DISABLED_FOR_TARGETS(ESP8266, ESP32) // This testcase for ESP32S2
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#include "soc/system_reg.h"
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static const char *TAG = "test_adc";
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#define PLATFORM_SELECT (1) //0: pxp; 1: chip
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#if (PLATFORM_SELECT == 0) //PXP platform
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#include "soc/apb_ctrl_reg.h"
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#define SET_BREAK_POINT(flag) REG_WRITE(APB_CTRL_DATE_REG, flag)
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//PXP clk is slower.
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#define SYS_DELAY_TIME_MOM (1/40)
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#define RTC_SLOW_CLK_FLAG 1 // Slow clock is 32KHz.
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static void test_pxp_deinit_io(void)
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{
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for (int i = 0; i < 22; i++) {
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rtc_gpio_init(i);
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}
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}
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#else
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//PXP clk is slower.
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#define SET_BREAK_POINT(flag)
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#define SYS_DELAY_TIME_MOM (1)
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#define RTC_SLOW_CLK_FLAG 0 // Slow clock is 32KHz.
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#endif
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#define ADC_REG_BASE_TEST() ({ \
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TEST_ASSERT_EQUAL_UINT32(REG_GET_FIELD(APB_SARADC_APB_CTRL_DATE_REG, APB_SARADC_APB_CTRL_DATE), APB_SARADC.apb_ctrl_date); \
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TEST_ASSERT_EQUAL_UINT32(REG_GET_FIELD(SENS_SARDATE_REG, SENS_SAR_DATE), SENS.sardate.sar_date); \
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TEST_ASSERT_EQUAL_UINT32(REG_GET_FIELD(RTC_IO_DATE_REG, RTC_IO_IO_DATE), RTCIO.date.date); \
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})
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#define TEST_ADC_TRIGGER_INTERVAL_DEFAULT (40)
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#define TEST_ADC_COUNT_NUM (10)
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#define TEST_ADC_CHANNEL (10)
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static adc_channel_t adc_list[TEST_ADC_CHANNEL] = {
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ADC_CHANNEL_0,
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ADC_CHANNEL_1,
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ADC_CHANNEL_2,
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ADC_CHANNEL_3,
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ADC_CHANNEL_4,
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ADC_CHANNEL_5,
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ADC_CHANNEL_6,
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ADC_CHANNEL_7,
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ADC_CHANNEL_8,
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ADC_CHANNEL_9,
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};
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/* For ESP32S2, it should use same atten, or, it will have error. */
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// #define TEST_ADC_ATTEN_DEFAULT (ADC_ATTEN_11db)
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static adc_atten_t adc_atten[ADC_ATTEN_MAX] = {
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ADC_ATTEN_DB_0,
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ADC_ATTEN_DB_2_5,
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ADC_ATTEN_DB_6,
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ADC_ATTEN_DB_11
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};
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/*******************************************/
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/** SPI DMA INIT CODE */
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/*******************************************/
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extern esp_err_t adc_digi_reset(void);
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typedef struct dma_link {
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struct {
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uint32_t size : 12; //the size of buf, must be able to be divisible by 4
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uint32_t length: 12; //in link,
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uint32_t reversed: 6; //reversed
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uint32_t eof: 1; //if this dma link is the last one, you shoule set this bit 1.
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uint32_t owner: 1; //the owner of buf, bit 1 : DMA, bit 0 : CPU.
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} des;
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uint8_t *buf; //the pointer of buf
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struct dma_link *pnext; //point to the next dma linker, if this link is the last one, set it NULL.
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} dma_link_t;
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/* Work mode.
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* sigle: eof_num;
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* double: SAR_EOF_NUMBER/2;
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* alter: eof_num;
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* */
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#define SAR_SIMPLE_NUM 64
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#define SAR_DMA_DATA_SIZE(unit, sample_num) (SAR_EOF_NUMBER(unit, sample_num) * 2) // 1 adc -> 2 byte
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#define SAR_EOF_NUMBER(unit, sample_num) ((sample_num) * (unit))
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#define SAR_MEAS_LIMIT_NUM(unit, sample_num) (SAR_EOF_NUMBER(unit, sample_num) / unit)
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static uint8_t link_buf[2][SAR_DMA_DATA_SIZE(2, SAR_SIMPLE_NUM)] = {0};
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static dma_link_t dma1;
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static dma_link_t dma2;
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static void dma_linker_init(adc_unit_t adc, bool is_loop)
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{
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dma1.des.eof = 0;
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dma1.des.owner = 1;
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dma1.pnext = &dma2;
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dma1.des.size = SAR_DMA_DATA_SIZE((adc > 2) ? 2 : 1, SAR_SIMPLE_NUM);
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dma1.des.length = 0; //For input buffer, this field is no use.
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dma1.buf = &link_buf[0][0];
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dma2.des.eof = 1;
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dma2.des.owner = 1;
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if (is_loop) {
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dma2.pnext = &dma1;
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} else {
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dma2.pnext = NULL;
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}
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dma2.des.size = SAR_DMA_DATA_SIZE((adc > 2) ? 2 : 1, SAR_SIMPLE_NUM);
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dma2.des.length = 0; //For input buffer, this field is no use.
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dma2.buf = &link_buf[1][0];
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REG_SET_BIT(DPORT_PERIP_CLK_EN_REG, DPORT_APB_SARADC_CLK_EN_M);
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REG_SET_BIT(DPORT_PERIP_CLK_EN_REG, DPORT_SPI3_DMA_CLK_EN_M);
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REG_SET_BIT(DPORT_PERIP_CLK_EN_REG, DPORT_SPI3_CLK_EN);
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REG_CLR_BIT(DPORT_PERIP_RST_EN_REG, DPORT_SPI3_DMA_RST_M);
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REG_CLR_BIT(DPORT_PERIP_RST_EN_REG, DPORT_SPI3_RST_M);
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uint32_t dma_pointer = (uint32_t)&dma1;
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SET_PERI_REG_BITS(SPI_DMA_IN_LINK_REG(3), SPI_INLINK_ADDR, dma_pointer, 0);
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REG_SET_BIT(SPI_DMA_IN_LINK_REG(3), SPI_INLINK_START);
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REG_CLR_BIT(SPI_DMA_IN_LINK_REG(3), SPI_INLINK_STOP);
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REG_SET_BIT(SPI_DMA_INT_ENA_REG(3), SPI_IN_SUC_EOF_INT_ENA);
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printf("reg addr 0x%08x 0x%08x \n", SPI_DMA_IN_LINK_REG(3), dma_pointer);
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}
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static void dma_linker_restart(void)
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{
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REG_SET_BIT(SPI_DMA_IN_LINK_REG(3), SPI_INLINK_STOP);
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REG_CLR_BIT(SPI_DMA_IN_LINK_REG(3), SPI_INLINK_START);
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REG_SET_BIT(SPI_DMA_IN_LINK_REG(3), SPI_INLINK_RESTART_M);
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REG_CLR_BIT(SPI_DMA_IN_LINK_REG(3), SPI_INLINK_RESTART_M);
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REG_SET_BIT(SPI_DMA_IN_LINK_REG(3), SPI_INLINK_START);
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REG_CLR_BIT(SPI_DMA_IN_LINK_REG(3), SPI_INLINK_STOP);
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adc_digi_reset();
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}
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/*******************************************/
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/** SPI DMA INIT CODE END */
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/*******************************************/
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/**
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* TEST TOOLS
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* Note: internal pullup/pulldown is weak energy. if enabled WiFi, it should be need outside pullup/pulldown.
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*/
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#define ADC_GET_IO_NUM(periph, channel) (adc_channel_io_map[periph][channel])
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static void adc_fake_tie_middle(adc_unit_t adc)
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{
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if (adc & ADC_UNIT_1) {
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for (int i = 0; i < TEST_ADC_CHANNEL; i++) {
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adc_gpio_init(ADC_UNIT_1, adc_list[i]);
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TEST_ESP_OK(rtc_gpio_pullup_en(ADC_GET_IO_NUM(0, adc_list[i])));
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TEST_ESP_OK(rtc_gpio_pulldown_en(ADC_GET_IO_NUM(0, adc_list[i])));
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}
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}
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if (adc & ADC_UNIT_2) {
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for (int i = 0; i < TEST_ADC_CHANNEL; i++) {
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adc_gpio_init(ADC_UNIT_2, adc_list[i]);
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TEST_ESP_OK(rtc_gpio_pullup_en(ADC_GET_IO_NUM(1, adc_list[i])));
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TEST_ESP_OK(rtc_gpio_pulldown_en(ADC_GET_IO_NUM(1, adc_list[i])));
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}
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}
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vTaskDelay(10 / portTICK_RATE_MS); // To wait stable of IO.
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}
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static void adc_fake_tie_high(adc_unit_t adc)
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{
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if (adc & ADC_UNIT_1) {
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for (int i = 0; i < TEST_ADC_CHANNEL; i++) {
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adc_gpio_init(ADC_UNIT_1, adc_list[i]);
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TEST_ESP_OK(rtc_gpio_pullup_en(ADC_GET_IO_NUM(0, adc_list[i])));
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TEST_ESP_OK(rtc_gpio_pulldown_dis(ADC_GET_IO_NUM(0, adc_list[i])));
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}
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}
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if (adc & ADC_UNIT_2) {
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for (int i = 0; i < TEST_ADC_CHANNEL; i++) {
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adc_gpio_init(ADC_UNIT_2, adc_list[i]);
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TEST_ESP_OK(rtc_gpio_pullup_en(ADC_GET_IO_NUM(1, adc_list[i])));
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TEST_ESP_OK(rtc_gpio_pulldown_dis(ADC_GET_IO_NUM(1, adc_list[i])));
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}
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}
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vTaskDelay(10 / portTICK_RATE_MS); // To wait stable of IO.
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}
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static void adc_fake_tie_low(adc_unit_t adc)
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{
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if (adc & ADC_UNIT_1) {
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for (int i = 0; i < TEST_ADC_CHANNEL; i++) {
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adc_gpio_init(ADC_UNIT_1, adc_list[i]);
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TEST_ESP_OK(rtc_gpio_pullup_dis(ADC_GET_IO_NUM(0, adc_list[i])));
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TEST_ESP_OK(rtc_gpio_pulldown_en(ADC_GET_IO_NUM(0, adc_list[i])));
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}
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}
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if (adc & ADC_UNIT_2) {
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for (int i = 0; i < TEST_ADC_CHANNEL; i++) {
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adc_gpio_init(ADC_UNIT_2, adc_list[i]);
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TEST_ESP_OK(rtc_gpio_pullup_dis(ADC_GET_IO_NUM(1, adc_list[i])));
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TEST_ESP_OK(rtc_gpio_pulldown_en(ADC_GET_IO_NUM(1, adc_list[i])));
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}
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}
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vTaskDelay(10 / portTICK_RATE_MS); // To wait stable of IO.
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}
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static void adc_io_normal(adc_unit_t adc)
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{
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if (adc & ADC_UNIT_1) {
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for (int i = 0; i < TEST_ADC_CHANNEL; i++) {
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adc_gpio_init(ADC_UNIT_1, adc_list[i]);
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}
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}
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if (adc & ADC_UNIT_2) {
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for (int i = 0; i < TEST_ADC_CHANNEL; i++) {
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adc_gpio_init(ADC_UNIT_2, adc_list[i]);
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}
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}
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vTaskDelay(10 / portTICK_RATE_MS); // To wait stable of IO.
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}
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#define DEBUG_CHECK_ENABLE 0
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#define DEBUG_PRINT_ENABLE 1
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#define DEBUG_CHECK_ERROR 100
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static esp_err_t adc_dma_data_check(adc_unit_t adc, int ideal_level)
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{
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#if DEBUG_CHECK_ENABLE
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int unit_old = 1;
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int ch_cnt = 0;
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#endif
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for (int cnt = 0; cnt < 2; cnt++) {
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ets_printf("\n[%s] link_buf[%d]: \n", __func__, cnt % 2);
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for (int i = 0; i < SAR_DMA_DATA_SIZE((adc > 2) ? 2 : 1, SAR_SIMPLE_NUM); i++, i++) {
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uint16_t h = link_buf[cnt % 2][i + 1], l = link_buf[cnt % 2][i];
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uint16_t temp = (h << 8 | l);
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adc_digi_output_data_t *data = (adc_digi_output_data_t *)&temp;
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if (adc > ADC_UNIT_2) { //ADC_ENCODE_11BIT
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#if DEBUG_PRINT_ENABLE
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if (i % 16 == 0) {
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ets_printf("\n");
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}
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ets_printf("[%d_%d_%04x] ", data->type2.unit, data->type2.channel, data->type2.data);
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#endif
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#if DEBUG_CHECK_ENABLE
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TEST_ASSERT_NOT_EQUAL(unit_old, data->type2.unit);
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unit_old = data->type2.unit;
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if (data->type2.channel > ADC_CHANNEL_MAX) {
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printf("Data invalid [%d]\n", data->type2.channel);
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continue;
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}
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int cur_ch = ((ch_cnt++ / 2) % TEST_ADC_CHANNEL);
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TEST_ASSERT_EQUAL( data->type2.channel, adc_list[cur_ch] );
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/*Check data channel unit*/
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if (ideal_level == 1) {
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TEST_ASSERT_INT_WITHIN( DEBUG_CHECK_ERROR, 0x7FF, data->type2.data );
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} else if (ideal_level == 0) {
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TEST_ASSERT_INT_WITHIN( DEBUG_CHECK_ERROR, 0, data->type2.data );
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} else {
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// middle vol
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}
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#endif
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} else { //ADC_ENCODE_12BIT
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#if DEBUG_PRINT_ENABLE
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if (i % 16 == 0) {
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ets_printf("\n");
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}
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ets_printf("[%d_%04x] ", data->type1.channel, data->type1.data);
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#endif
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#if DEBUG_CHECK_ENABLE
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/*Check data channel */
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if (ideal_level == 1) {
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if (data->type1.data != 0XFFF) {
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return ESP_FAIL;
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}
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} else if (ideal_level == 0) {
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if (data->type1.data != 0) {
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return ESP_FAIL;
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}
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} else {
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if (data->type1.data == 0 || data->type1.data == 0XFFF) {
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return ESP_FAIL;
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}
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}
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int cur_ch = ((i / 2) % TEST_ADC_CHANNEL);
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if (data->type1.channel != adc_list[cur_ch] ) {
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return ESP_FAIL;
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}
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#endif
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}
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link_buf[cnt % 2][i] = 0;
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link_buf[cnt % 2][i + 1] = 0;
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}
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ets_printf("\n");
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}
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return ESP_OK;
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}
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static esp_err_t adc_dma_data_multi_st_check(adc_unit_t adc)
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{
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ESP_LOGI(TAG, "adc IO fake tie low, test ...");
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adc_fake_tie_low(adc);
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TEST_ESP_OK( adc_digi_stop() );
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dma_linker_restart();
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REG_SET_BIT(SPI_DMA_INT_CLR_REG(3), SPI_IN_SUC_EOF_INT_CLR);
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TEST_ESP_OK( adc_digi_start() );
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while (0 == REG_GET_BIT(SPI_DMA_INT_ST_REG(3), SPI_IN_SUC_EOF_INT_ST)) {};
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REG_SET_BIT(SPI_DMA_INT_CLR_REG(3), SPI_IN_SUC_EOF_INT_CLR);
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if ( ESP_OK != adc_dma_data_check(adc, 0)) {
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return ESP_FAIL;
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}
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ESP_LOGI(TAG, "adc IO fake tie high, test ...");
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adc_fake_tie_high(adc);
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TEST_ESP_OK( adc_digi_stop() );
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dma_linker_restart();
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REG_SET_BIT(SPI_DMA_INT_CLR_REG(3), SPI_IN_SUC_EOF_INT_CLR);
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TEST_ESP_OK( adc_digi_start() );
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while (0 == REG_GET_BIT(SPI_DMA_INT_ST_REG(3), SPI_IN_SUC_EOF_INT_ST)) {};
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REG_SET_BIT(SPI_DMA_INT_CLR_REG(3), SPI_IN_SUC_EOF_INT_CLR);
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if ( ESP_OK != adc_dma_data_check(adc, 1)) {
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return ESP_FAIL;
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}
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ESP_LOGI(TAG, "adc IO fake tie middle, test ...");
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adc_fake_tie_middle(adc);
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TEST_ESP_OK( adc_digi_stop() );
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dma_linker_restart();
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REG_SET_BIT(SPI_DMA_INT_CLR_REG(3), SPI_IN_SUC_EOF_INT_CLR);
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TEST_ESP_OK( adc_digi_start() );
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while (0 == REG_GET_BIT(SPI_DMA_INT_ST_REG(3), SPI_IN_SUC_EOF_INT_ST)) {};
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REG_SET_BIT(SPI_DMA_INT_CLR_REG(3), SPI_IN_SUC_EOF_INT_CLR);
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if ( ESP_OK != adc_dma_data_check(adc, 2)) {
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return ESP_FAIL;
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}
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TEST_ESP_OK( adc_digi_stop() );
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adc_io_normal(adc);
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return ESP_OK;
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}
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#include "soc/apb_saradc_struct.h"
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/**
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* @brief Test the partten table setting. It's easy wrong.
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*
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* @param adc_n ADC unit.
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* @param in_partten_len The length of partten be set.
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* @param in_partten_len The channel number of the last message.
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*/
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static esp_err_t adc_check_patt_table(adc_unit_t adc, uint32_t in_partten_len, adc_channel_t in_last_ch)
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{
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esp_err_t ret = ESP_FAIL;
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uint8_t index = (in_partten_len - 1) / 4;
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uint8_t offset = 24 - ((in_partten_len - 1) % 4) * 8;
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uint32_t temp = 0, len;
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if (adc & ADC_UNIT_1) {
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len = APB_SARADC.ctrl.sar1_patt_len + 1;
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temp = APB_SARADC.sar1_patt_tab[index];
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printf("patt1 len %d\n", len);
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printf("patt1 0x%08x\n", APB_SARADC.sar1_patt_tab[0]);
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printf("patt1 0x%08x\n", APB_SARADC.sar1_patt_tab[1]);
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printf("patt1 0x%08x\n", APB_SARADC.sar1_patt_tab[2]);
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printf("patt1 0x%08x\n", APB_SARADC.sar1_patt_tab[3]);
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if (in_partten_len == len) {
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if (in_last_ch == (((temp >> (offset + 4))) & 0xf)) {
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ret = ESP_OK;
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}
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}
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}
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if (adc & ADC_UNIT_2) {
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len = APB_SARADC.ctrl.sar2_patt_len + 1;
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temp = APB_SARADC.sar2_patt_tab[index];
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printf("patt2 len %d\n", len);
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printf("patt2 0x%08x\n", APB_SARADC.sar2_patt_tab[0]);
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printf("patt2 0x%08x\n", APB_SARADC.sar2_patt_tab[1]);
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printf("patt2 0x%08x\n", APB_SARADC.sar2_patt_tab[2]);
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printf("patt2 0x%08x\n", APB_SARADC.sar2_patt_tab[3]);
|
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if (in_partten_len == len) {
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if (in_last_ch == (((temp >> (offset + 4))) & 0xf)) {
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ret = ESP_OK;
|
|
}
|
|
}
|
|
}
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return ret;
|
|
}
|
|
|
|
int test_adc_dig_dma_single_unit(adc_unit_t adc)
|
|
{
|
|
ESP_LOGI(TAG, " >> %s << ", __func__);
|
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ESP_LOGI(TAG, " >> adc unit: %x << ", adc);
|
|
|
|
TEST_ESP_OK( adc_digi_init() );
|
|
/* arbiter config */
|
|
adc_arbiter_t arb_cfg = {
|
|
.mode = ADC_ARB_MODE_FIX,
|
|
.dig_pri = 0,
|
|
.pwdet_pri = 2,
|
|
.rtc_pri = 1,
|
|
};
|
|
TEST_ESP_OK( adc_arbiter_config(ADC_UNIT_2, &arb_cfg) ); // If you want use force
|
|
|
|
adc_digi_config_t config = {
|
|
.conv_limit_en = false,
|
|
.conv_limit_num = 0,
|
|
.interval = TEST_ADC_TRIGGER_INTERVAL_DEFAULT,
|
|
.dig_clk.use_apll = 0, // APB clk
|
|
.dig_clk.div_num = 2, // 80 MHz / 160 = 500 KHz
|
|
.dig_clk.div_b = 1,
|
|
.dig_clk.div_a = 1,
|
|
.dma_eof_num = SAR_EOF_NUMBER((adc > 2) ? 2 : 1, SAR_SIMPLE_NUM),
|
|
};
|
|
/* Config pattern table */
|
|
adc_digi_pattern_table_t adc1_patt[TEST_ADC_CHANNEL] = {0};
|
|
adc_digi_pattern_table_t adc2_patt[TEST_ADC_CHANNEL] = {0};
|
|
if (adc & ADC_UNIT_1) {
|
|
config.adc1_pattern_len = TEST_ADC_CHANNEL;
|
|
config.adc1_pattern = adc1_patt;
|
|
for (int i = 0; i < TEST_ADC_CHANNEL; i++) {
|
|
adc1_patt[i].atten = adc_atten[i%ADC_ATTEN_MAX];
|
|
adc1_patt[i].channel = adc_list[i];
|
|
adc_gpio_init(ADC_UNIT_1, adc_list[i]);
|
|
}
|
|
}
|
|
if (adc & ADC_UNIT_2) {
|
|
config.adc2_pattern_len = TEST_ADC_CHANNEL;
|
|
config.adc2_pattern = adc2_patt;
|
|
for (int i = 0; i < TEST_ADC_CHANNEL; i++) {
|
|
adc2_patt[i].atten = adc_atten[i%ADC_ATTEN_MAX];
|
|
adc2_patt[i].channel = adc_list[i];
|
|
adc_gpio_init(ADC_UNIT_2, adc_list[i]);
|
|
}
|
|
}
|
|
if (adc == ADC_UNIT_1) {
|
|
config.conv_mode = ADC_CONV_SINGLE_UNIT_1;
|
|
config.format = ADC_DIGI_FORMAT_12BIT;
|
|
} else if (adc == ADC_UNIT_2) {
|
|
config.conv_mode = ADC_CONV_SINGLE_UNIT_2;
|
|
config.format = ADC_DIGI_FORMAT_12BIT;
|
|
} else if (adc == ADC_UNIT_BOTH) {
|
|
config.conv_mode = ADC_CONV_BOTH_UNIT;
|
|
config.format = ADC_DIGI_FORMAT_11BIT;
|
|
} else if (adc == ADC_UNIT_ALTER) {
|
|
config.conv_mode = ADC_CONV_ALTER_UNIT;
|
|
config.format = ADC_DIGI_FORMAT_11BIT;
|
|
}
|
|
TEST_ESP_OK( adc_digi_controller_config(&config) );
|
|
|
|
dma_linker_init(adc, false);
|
|
TEST_ESP_OK( adc_check_patt_table(adc, TEST_ADC_CHANNEL, adc_list[TEST_ADC_CHANNEL - 1]) );
|
|
|
|
TEST_ESP_OK( adc_digi_start() );
|
|
|
|
adc_dma_data_multi_st_check(adc);
|
|
|
|
return 0;
|
|
}
|
|
|
|
TEST_CASE("ADC DMA single read", "[ADC]")
|
|
{
|
|
test_adc_dig_dma_single_unit(ADC_UNIT_BOTH);
|
|
|
|
test_adc_dig_dma_single_unit(ADC_UNIT_ALTER);
|
|
|
|
test_adc_dig_dma_single_unit(ADC_UNIT_1);
|
|
|
|
test_adc_dig_dma_single_unit(ADC_UNIT_2);
|
|
}
|
|
|
|
#endif // !DISABLED_FOR_TARGETS(ESP8266, ESP32)
|