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https://github.com/espressif/esp-idf.git
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b957692888
These were previously placed on the stack, but the stack could be placed in RTC RAM which is not DMA capable.
107 lines
5.5 KiB
C
107 lines
5.5 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#define IDF_PERFORMANCE_MIN_AES_CBC_THROUGHPUT_MBSEC 43.0
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#define IDF_PERFORMANCE_MIN_AES_GCM_CRYPT_TAG_THROUGHPUT_MBSEC 30.0
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#define IDF_PERFORMANCE_MIN_AES_GCM_UPDATE_THROUGHPUT_MBSEC 2.1
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// SHA256 hardware throughput at 240MHz, threshold set lower than worst case
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#define IDF_PERFORMANCE_MIN_SHA256_THROUGHPUT_MBSEC 90.0
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// esp_sha() time to process 32KB of input data from RAM
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#define IDF_PERFORMANCE_MAX_TIME_SHA1_32KB 900
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#define IDF_PERFORMANCE_MAX_TIME_SHA512_32KB 900
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#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PUBLIC_OP 13500
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#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PRIVATE_OP 130000
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#define IDF_PERFORMANCE_MAX_RSA_3072KEY_PUBLIC_OP 36000
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#define IDF_PERFORMANCE_MAX_RSA_3072KEY_PRIVATE_OP 400000
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#define IDF_PERFORMANCE_MAX_RSA_4096KEY_PUBLIC_OP 62000
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#define IDF_PERFORMANCE_MAX_RSA_4096KEY_PRIVATE_OP 800000
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#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 32
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#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 30
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/*
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* Flash Performance value
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* 4 subsections: legacy, normal (new driver after v4.0), SPI1 (external but on SPI1), external (SPI2)
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* These thresholds are set to about 70% of the average test data, under certain condition.
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* Contact Espressif for details.
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*/
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#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_LEGACY_WR_4B
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//Great variation, use the 70% of min value
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#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_LEGACY_WR_4B 33300
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#endif
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#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_LEGACY_RD_4B
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// legacy config is much faster. use the 70% of slower configs
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#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_LEGACY_RD_4B (239*1000)
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#endif
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#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_LEGACY_WR_2KB
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// Weird data. Use 70% average of slower configs.
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#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_LEGACY_WR_2KB (546*1000)
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#endif
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#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_LEGACY_RD_2KB
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#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_LEGACY_RD_2KB (1191*1000)
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#endif
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#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_LEGACY_ERASE
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//erase performance is highly depending on the chip vendor. Use 70% of the minimal value.
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#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_LEGACY_ERASE 19500
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#endif
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#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_WR_4B
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//release config is much faster than other configs. Use 70% average of other configs
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#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_WR_4B 46300
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#endif
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#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_RD_4B
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#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_RD_4B (249*1000)
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#endif
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#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_WR_2KB
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#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_WR_2KB (851*1000)
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#endif
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#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_RD_2KB
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#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_RD_2KB (11480*1000)
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#endif
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#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_ERASE
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//erase performance is highly depending on the chip vendor. Use 70% of the minimal value.
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#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_ERASE 40100
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#endif
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#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_SPI1_WR_4B
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#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_SPI1_WR_4B 30500
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#endif
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#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_SPI1_RD_4B
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#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_SPI1_RD_4B (183*1000)
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#endif
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#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_SPI1_WR_2KB
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#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_SPI1_WR_2KB (474*1000)
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#endif
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#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_SPI1_RD_2KB
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#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_SPI1_RD_2KB (1283*1000)
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#endif
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#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_SPI1_ERASE
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//erase performance is highly depending on the chip vendor. Use 70% of the minimal value.
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#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_SPI1_ERASE 44100
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#endif
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#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_WR_4B
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#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_WR_4B 47800
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#endif
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#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_4B
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#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_4B (252*1000)
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#endif
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#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_WR_2KB
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// write with large RAM buffer tests has lower performance value than normal performance tests
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#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_WR_2KB (398*1000)
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#endif
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#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_2KB
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#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_2KB (1204*1000)
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#endif
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#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_ERASE
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//erase performance is highly depending on the chip vendor. Use 70% of the minimal value.
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#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_ERASE 22100
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#endif
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