mirror of
https://github.com/espressif/esp-idf.git
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40f3bc2e57
- Support SOC ROOT clock source switch - Support CPU frequency change - Support RTC SLOW clock source switch - Support RTC SLOW clock + RC FAST calibration - Remove FPGA build
226 lines
7.5 KiB
C
226 lines
7.5 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include <string.h>
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#include <sys/param.h>
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#include <sys/lock.h>
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#include "freertos/FreeRTOS.h"
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#include "esp_attr.h"
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#include "soc/rtc.h"
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#include "soc/soc_caps.h"
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#include "esp_rom_caps.h"
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#include "esp_rom_sys.h"
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#include "esp_private/esp_clk.h"
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#include "hal/clk_tree_ll.h"
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#if CONFIG_IDF_TARGET_ESP32
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#include "esp32/rom/rtc.h"
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#include "esp32/rtc.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/rom/rtc.h"
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#include "esp32s2/rtc.h"
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#elif CONFIG_IDF_TARGET_ESP32S3
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#include "esp32s3/rom/rtc.h"
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#include "esp32s3/rtc.h"
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#elif CONFIG_IDF_TARGET_ESP32C3
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#include "esp32c3/rom/rtc.h"
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#include "esp32c3/rtc.h"
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#elif CONFIG_IDF_TARGET_ESP32C2
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#include "esp32c2/rom/rtc.h"
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#include "esp32c2/rtc.h"
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#elif CONFIG_IDF_TARGET_ESP32C6
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#include "esp32c6/rom/rtc.h"
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#include "esp32c6/rtc.h"
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#elif CONFIG_IDF_TARGET_ESP32C61 //TODO: IDF-9526, refactor this
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#include "esp32c61/rom/rtc.h"
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#include "esp32c61/rtc.h"
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#elif CONFIG_IDF_TARGET_ESP32H2
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#include "esp32h2/rom/rtc.h"
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#include "esp32h2/rtc.h"
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#elif CONFIG_IDF_TARGET_ESP32P4
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#include "esp32p4/rom/rtc.h"
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#include "esp32p4/rtc.h"
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#endif
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#define MHZ (1000000)
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// g_ticks_us defined in ROMs for PRO and APP CPU
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extern uint32_t g_ticks_per_us_pro;
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static portMUX_TYPE s_esp_rtc_time_lock = portMUX_INITIALIZER_UNLOCKED;
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#if SOC_RTC_MEM_SUPPORTED
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typedef struct {
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uint64_t rtc_time_us;
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uint64_t rtc_last_ticks;
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uint32_t reserve;
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uint32_t checksum;
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} retain_mem_t;
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_Static_assert(sizeof(retain_mem_t) == 24, "retain_mem_t must be 24 bytes");
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_Static_assert(offsetof(retain_mem_t, checksum) == sizeof(retain_mem_t) - sizeof(uint32_t), "Wrong offset for checksum field in retain_mem_t structure");
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static __attribute__((section(".rtc_timer_data_in_rtc_mem"))) retain_mem_t s_rtc_timer_retain_mem;
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static uint32_t calc_checksum(void)
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{
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uint32_t checksum = 0;
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uint32_t *data = (uint32_t*) &s_rtc_timer_retain_mem;
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for (uint32_t i = 0; i < (sizeof(retain_mem_t) - sizeof(s_rtc_timer_retain_mem.checksum)) / 4; i++) {
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checksum = ((checksum << 5) - checksum) ^ data[i];
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}
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return checksum;
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}
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#define IS_RETAIN_MEM_VALID() (s_rtc_timer_retain_mem.checksum == calc_checksum())
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#endif // SOC_RTC_MEM_SUPPORTED
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inline static int IRAM_ATTR s_get_cpu_freq_mhz(void)
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{
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#if ESP_ROM_GET_CLK_FREQ
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return esp_rom_get_cpu_ticks_per_us();
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#else
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return g_ticks_per_us_pro;
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#endif
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}
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int IRAM_ATTR esp_clk_cpu_freq(void)
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{
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return s_get_cpu_freq_mhz() * MHZ;
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}
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int IRAM_ATTR esp_clk_apb_freq(void)
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{
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// TODO: IDF-5173 Require cleanup, implementation should be unified
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#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
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return rtc_clk_apb_freq_get();
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#else
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return MIN(s_get_cpu_freq_mhz() * MHZ, APB_CLK_FREQ);
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#endif
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}
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int IRAM_ATTR esp_clk_xtal_freq(void)
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{
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return rtc_clk_xtal_freq_get() * MHZ;
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}
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uint64_t esp_rtc_get_time_us(void)
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{
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portENTER_CRITICAL_SAFE(&s_esp_rtc_time_lock);
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const uint32_t cal = esp_clk_slowclk_cal_get();
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#if SOC_RTC_MEM_SUPPORTED
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static bool first_call = true;
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if (cal == 0 || (first_call && !IS_RETAIN_MEM_VALID())) {
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/*
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If cal is 0, then this is the first power-up. Cal is keeping valid
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after reboot and deepsleep. If s_rtc_timer_retain_mem is invalid, it means
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that something unexpected happened (the structure was moved around
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after OTA update). To keep the system time valid even after OTA we
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reset the s_rtc_timer_retain_mem. But the resetting can also lead to some
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drift of the system time, because only the last current calibration
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value will be applied to all rtc ticks. To mitigate this effect you
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might need updating of the system time (via SNTP).
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*/
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memset(&s_rtc_timer_retain_mem, 0, sizeof(retain_mem_t));
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}
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first_call = false;
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const uint64_t rtc_this_ticks = rtc_time_get();
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const uint64_t ticks = rtc_this_ticks - s_rtc_timer_retain_mem.rtc_last_ticks;
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#else
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const uint64_t ticks = rtc_time_get();
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#endif
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/* RTC counter result is up to 2^48, calibration factor is up to 2^24,
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* for a 32kHz clock. We need to calculate (assuming no overflow):
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* (ticks * cal) >> RTC_CLK_CAL_FRACT
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*
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* An overflow in the (ticks * cal) multiplication would cause time to
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* wrap around after approximately 13 days, which is probably not enough
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* for some applications.
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* Therefore multiplication is split into two terms, for the lower 32-bit
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* and the upper 16-bit parts of "ticks", i.e.:
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* ((ticks_low + 2^32 * ticks_high) * cal) >> RTC_CLK_CAL_FRACT
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*/
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const uint64_t ticks_low = ticks & UINT32_MAX;
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const uint64_t ticks_high = ticks >> 32;
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const uint64_t delta_time_us = ((ticks_low * cal) >> RTC_CLK_CAL_FRACT) +
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((ticks_high * cal) << (32 - RTC_CLK_CAL_FRACT));
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#if SOC_RTC_MEM_SUPPORTED
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s_rtc_timer_retain_mem.rtc_time_us += delta_time_us;
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s_rtc_timer_retain_mem.rtc_last_ticks = rtc_this_ticks;
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s_rtc_timer_retain_mem.checksum = calc_checksum();
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uint64_t esp_rtc_time_us = s_rtc_timer_retain_mem.rtc_time_us;
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portEXIT_CRITICAL_SAFE(&s_esp_rtc_time_lock);
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return esp_rtc_time_us;
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#else
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uint64_t esp_rtc_time_us = delta_time_us + clk_ll_rtc_slow_load_rtc_fix_us();
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portEXIT_CRITICAL_SAFE(&s_esp_rtc_time_lock);
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return esp_rtc_time_us;
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#endif
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}
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void esp_clk_slowclk_cal_set(uint32_t new_cal)
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{
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#if defined(CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER)
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/* To force monotonic time values even when clock calibration value changes,
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* we adjust esp_rtc_time
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*/
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#if SOC_RTC_MEM_SUPPORTED
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esp_rtc_get_time_us();
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#else
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portENTER_CRITICAL_SAFE(&s_esp_rtc_time_lock);
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uint32_t old_cal = clk_ll_rtc_slow_load_cal();
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if (old_cal != 0) {
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/**
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* The logic of time correction is:
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* old_rtc_us = ticks * old_cal >> RTC_CLK_CAL_FRACT + old_fix_us
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* new_rtc_us = ticks * new_cal >> RTC_CLK_CAL_FRACT + new_fix_us
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*
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* Keep "old_rtc_us == new_rtc_us" to make time monotonically increasing,
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* then we can get new_fix_us:
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* new_fix_us = (ticks * old_cal >> RTC_CLK_CAL_FRACT + old_fix_us) - (ticks * new_cal >> RTC_CLK_CAL_FRACT)
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*/
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uint64_t ticks = rtc_time_get();
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const uint64_t ticks_low = ticks & UINT32_MAX;
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const uint64_t ticks_high = ticks >> 32;
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uint64_t old_fix_us = clk_ll_rtc_slow_load_rtc_fix_us();
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uint64_t new_fix_us;
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old_fix_us += ((ticks_low * old_cal) >> RTC_CLK_CAL_FRACT) + ((ticks_high * old_cal) << (32 - RTC_CLK_CAL_FRACT));
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new_fix_us = ((ticks_low * new_cal) >> RTC_CLK_CAL_FRACT) + ((ticks_high * new_cal) << (32 - RTC_CLK_CAL_FRACT));
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new_fix_us = old_fix_us - new_fix_us;
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clk_ll_rtc_slow_store_rtc_fix_us(new_fix_us);
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}
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portEXIT_CRITICAL_SAFE(&s_esp_rtc_time_lock);
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#endif // SOC_RTC_MEM_SUPPORTED
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#endif // CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER
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clk_ll_rtc_slow_store_cal(new_cal);
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}
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uint32_t esp_clk_slowclk_cal_get(void)
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{
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return clk_ll_rtc_slow_load_cal();
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}
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uint64_t esp_clk_rtc_time(void)
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{
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#ifdef CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER
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return esp_rtc_get_time_us();
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#else
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return 0;
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#endif
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}
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void esp_clk_private_lock(void)
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{
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portENTER_CRITICAL(&s_esp_rtc_time_lock);
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}
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void esp_clk_private_unlock(void)
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{
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portEXIT_CRITICAL(&s_esp_rtc_time_lock);
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}
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