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586 lines
22 KiB
C
586 lines
22 KiB
C
/**
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** I3C_SLV_CONFIG_REG register
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* NA
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*/
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#define I3C_SLV_CONFIG_REG (DR_REG_I3C_SLV_BASE + 0x4)
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/** I3C_SLV_SLVENA : R/W; bitpos: [0]; default: 1;
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* 1: allow the slave to operate on i2c or i3c bus. 0: the slave will ignore the bus.
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* This should be not set until registers such as PARTNO, IDEXT and the like are set
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* 1st -if used- since they impact data to the master
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*/
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#define I3C_SLV_SLVENA (BIT(0))
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#define I3C_SLV_SLVENA_M (I3C_SLV_SLVENA_V << I3C_SLV_SLVENA_S)
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#define I3C_SLV_SLVENA_V 0x00000001U
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#define I3C_SLV_SLVENA_S 0
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/** I3C_SLV_NACK : R/W; bitpos: [1]; default: 0;
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* 1:the slave will NACK all requests to it except CCC broadcast. This should be used
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* with caution as the Master may determine the slave is missing if overused.
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*/
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#define I3C_SLV_NACK (BIT(1))
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#define I3C_SLV_NACK_M (I3C_SLV_NACK_V << I3C_SLV_NACK_S)
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#define I3C_SLV_NACK_V 0x00000001U
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#define I3C_SLV_NACK_S 1
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/** I3C_SLV_MATCHSS : R/W; bitpos: [2]; default: 0;
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* 1: the START and STOP sticky STATUS bits will only be set if MATCHED is set..This
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* allows START and STOP to be used to detect end of a message to /from this slave.
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*/
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#define I3C_SLV_MATCHSS (BIT(2))
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#define I3C_SLV_MATCHSS_M (I3C_SLV_MATCHSS_V << I3C_SLV_MATCHSS_S)
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#define I3C_SLV_MATCHSS_V 0x00000001U
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#define I3C_SLV_MATCHSS_S 2
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/** I3C_SLV_S0IGNORE : R/W; bitpos: [3]; default: 0;
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* If 1, the Slave will not detect S0 or S1 errors and so not lock up waiting on an
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* Exit Pattern. This should only be used when the bus will not use HDR.
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*/
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#define I3C_SLV_S0IGNORE (BIT(3))
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#define I3C_SLV_S0IGNORE_M (I3C_SLV_S0IGNORE_V << I3C_SLV_S0IGNORE_S)
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#define I3C_SLV_S0IGNORE_V 0x00000001U
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#define I3C_SLV_S0IGNORE_S 3
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/** I3C_SLV_DDROK : R/W; bitpos: [4]; default: 0;
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* NA
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*/
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#define I3C_SLV_DDROK (BIT(4))
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#define I3C_SLV_DDROK_M (I3C_SLV_DDROK_V << I3C_SLV_DDROK_S)
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#define I3C_SLV_DDROK_V 0x00000001U
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#define I3C_SLV_DDROK_S 4
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/** I3C_SLV_IDRAND : R/W; bitpos: [8]; default: 0;
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* NA
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*/
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#define I3C_SLV_IDRAND (BIT(8))
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#define I3C_SLV_IDRAND_M (I3C_SLV_IDRAND_V << I3C_SLV_IDRAND_S)
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#define I3C_SLV_IDRAND_V 0x00000001U
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#define I3C_SLV_IDRAND_S 8
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/** I3C_SLV_OFFLINE : R/W; bitpos: [9]; default: 0;
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* NA
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*/
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#define I3C_SLV_OFFLINE (BIT(9))
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#define I3C_SLV_OFFLINE_M (I3C_SLV_OFFLINE_V << I3C_SLV_OFFLINE_S)
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#define I3C_SLV_OFFLINE_V 0x00000001U
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#define I3C_SLV_OFFLINE_S 9
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/** I3C_SLV_BAMATCH : R/W; bitpos: [23:16]; default: 47;
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* Bus Available condition match value for current ???Slow clock???. This provides the
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* count of the slow clock to count out 1us (or more) to allow an IBI to drive SDA Low
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* when the Master is not doing so. The max width , and so max value, is controlled by
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* the block. Only if enabled for events such IBI or MR or HJ, and if enabled to
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* provide this as a register. With is limited to CLK_SLOW_BITS
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*/
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#define I3C_SLV_BAMATCH 0x000000FFU
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#define I3C_SLV_BAMATCH_M (I3C_SLV_BAMATCH_V << I3C_SLV_BAMATCH_S)
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#define I3C_SLV_BAMATCH_V 0x000000FFU
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#define I3C_SLV_BAMATCH_S 16
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/** I3C_SLV_SADDR : R/W; bitpos: [31:25]; default: 0;
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* If allowed by the block:sets i2c 7 bits static address,else should be 0. If enabled
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* to use one and to be provided by SW. Block may provide in HW as well.
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*/
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#define I3C_SLV_SADDR 0x0000007FU
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#define I3C_SLV_SADDR_M (I3C_SLV_SADDR_V << I3C_SLV_SADDR_S)
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#define I3C_SLV_SADDR_V 0x0000007FU
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#define I3C_SLV_SADDR_S 25
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/** I3C_SLV_STATUS_REG register
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* NA
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*/
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#define I3C_SLV_STATUS_REG (DR_REG_I3C_SLV_BASE + 0x8)
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/** I3C_SLV_STNOTSTOP : RO; bitpos: [0]; default: 0;
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* Is 1 if bus is busy(activity) and 0 when in a STOP condition. Other bits may also
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* set when busy. Note that this can also be true from an S0 or S1 error, which waits
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* for an Exit Pattern.
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*/
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#define I3C_SLV_STNOTSTOP (BIT(0))
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#define I3C_SLV_STNOTSTOP_M (I3C_SLV_STNOTSTOP_V << I3C_SLV_STNOTSTOP_S)
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#define I3C_SLV_STNOTSTOP_V 0x00000001U
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#define I3C_SLV_STNOTSTOP_S 0
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/** I3C_SLV_STMSG : RO; bitpos: [1]; default: 0;
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* Is 1 if this bus Slave is listening to the bus traffic or repsonding, If
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* STNOSTOP=1, then this will be 0 when a non-matching address seen until next
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* respeated START it STOP.
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*/
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#define I3C_SLV_STMSG (BIT(1))
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#define I3C_SLV_STMSG_M (I3C_SLV_STMSG_V << I3C_SLV_STMSG_S)
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#define I3C_SLV_STMSG_V 0x00000001U
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#define I3C_SLV_STMSG_S 1
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/** I3C_SLV_STCCCH : RO; bitpos: [2]; default: 0;
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* Is 1 if a CCC message is being handled automatically.
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*/
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#define I3C_SLV_STCCCH (BIT(2))
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#define I3C_SLV_STCCCH_M (I3C_SLV_STCCCH_V << I3C_SLV_STCCCH_S)
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#define I3C_SLV_STCCCH_V 0x00000001U
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#define I3C_SLV_STCCCH_S 2
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/** I3C_SLV_STREQRD : RO; bitpos: [3]; default: 0;
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* 1 if the req in process is an sdr read from this slave or an IBI is being pushed
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* out,
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*/
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#define I3C_SLV_STREQRD (BIT(3))
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#define I3C_SLV_STREQRD_M (I3C_SLV_STREQRD_V << I3C_SLV_STREQRD_S)
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#define I3C_SLV_STREQRD_V 0x00000001U
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#define I3C_SLV_STREQRD_S 3
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/** I3C_SLV_STREQWR : RO; bitpos: [4]; default: 0;
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* NA
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*/
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#define I3C_SLV_STREQWR (BIT(4))
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#define I3C_SLV_STREQWR_M (I3C_SLV_STREQWR_V << I3C_SLV_STREQWR_S)
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#define I3C_SLV_STREQWR_V 0x00000001U
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#define I3C_SLV_STREQWR_S 4
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/** I3C_SLV_STDAA : RO; bitpos: [5]; default: 0;
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* NA
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*/
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#define I3C_SLV_STDAA (BIT(5))
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#define I3C_SLV_STDAA_M (I3C_SLV_STDAA_V << I3C_SLV_STDAA_S)
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#define I3C_SLV_STDAA_V 0x00000001U
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#define I3C_SLV_STDAA_S 5
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/** I3C_SLV_STHDR : RO; bitpos: [6]; default: 0;
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* NA
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*/
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#define I3C_SLV_STHDR (BIT(6))
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#define I3C_SLV_STHDR_M (I3C_SLV_STHDR_V << I3C_SLV_STHDR_S)
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#define I3C_SLV_STHDR_V 0x00000001U
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#define I3C_SLV_STHDR_S 6
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/** I3C_SLV_START : R/W; bitpos: [8]; default: 0;
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* NA
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*/
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#define I3C_SLV_START (BIT(8))
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#define I3C_SLV_START_M (I3C_SLV_START_V << I3C_SLV_START_S)
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#define I3C_SLV_START_V 0x00000001U
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#define I3C_SLV_START_S 8
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/** I3C_SLV_MATCHED : R/W; bitpos: [9]; default: 0;
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* NA
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*/
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#define I3C_SLV_MATCHED (BIT(9))
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#define I3C_SLV_MATCHED_M (I3C_SLV_MATCHED_V << I3C_SLV_MATCHED_S)
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#define I3C_SLV_MATCHED_V 0x00000001U
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#define I3C_SLV_MATCHED_S 9
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/** I3C_SLV_STOP : R/W; bitpos: [10]; default: 0;
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* NA
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*/
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#define I3C_SLV_STOP (BIT(10))
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#define I3C_SLV_STOP_M (I3C_SLV_STOP_V << I3C_SLV_STOP_S)
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#define I3C_SLV_STOP_V 0x00000001U
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#define I3C_SLV_STOP_S 10
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/** I3C_SLV_RXPEND : RO; bitpos: [11]; default: 0;
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* Receiving a message from master,which is not being handled by block(not a CCC
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* internally processed). For all but External FIFO, this uses DATACTRL RXTRIG, which
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* defaults to not-empty. If DMA is enabled for RX, DMA will be signaled as well. Will
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* self-clear if data is read(FIFO and non-FIFO)
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*/
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#define I3C_SLV_RXPEND (BIT(11))
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#define I3C_SLV_RXPEND_M (I3C_SLV_RXPEND_V << I3C_SLV_RXPEND_S)
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#define I3C_SLV_RXPEND_V 0x00000001U
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#define I3C_SLV_RXPEND_S 11
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/** I3C_SLV_TXNOTFULL : RO; bitpos: [12]; default: 0;
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* Is 1 when the To-bus buffer/FIFO can accept more data to go out. Defau:1. For all
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* but External FIFO, this uses DATACTRL TXTRIG,which defaults to not-full. If DMA is
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* enabled for TX, it will also be signaled to provide more.
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*/
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#define I3C_SLV_TXNOTFULL (BIT(12))
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#define I3C_SLV_TXNOTFULL_M (I3C_SLV_TXNOTFULL_V << I3C_SLV_TXNOTFULL_S)
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#define I3C_SLV_TXNOTFULL_V 0x00000001U
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#define I3C_SLV_TXNOTFULL_S 12
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/** I3C_SLV_DACHG : R/W; bitpos: [13]; default: 0;
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* The Slv Dynamic Address has been assigned, reassigned, or reset(lost) and is now in
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* that state of being valid or none. Actual DA can be seen in the DYNADDR register.
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* Note that this will also be used when MAP Auto feature is configured. This will be
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* changing one or more MAP items. See DYNADDR and/or MAPCTRLn. DYNAADDR for the main
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* DA(0) will indicate if last change was due to Auto MAP.
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*/
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#define I3C_SLV_DACHG (BIT(13))
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#define I3C_SLV_DACHG_M (I3C_SLV_DACHG_V << I3C_SLV_DACHG_S)
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#define I3C_SLV_DACHG_V 0x00000001U
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#define I3C_SLV_DACHG_S 13
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/** I3C_SLV_CCC : R/W; bitpos: [14]; default: 0;
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* A common -command-code(CCC), not handled by block, has been received. This acts
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* differently between: *Broadcasted ones, which will then also correspond with RXPEND
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* and the 1st byte will be the CCC(command) . *Direct ones, which may never be
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* directed to this device. If it is, then the TXSEND or RXPEND will be triggered
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* with this end the RXPEND will contain the command.
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*/
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#define I3C_SLV_CCC (BIT(14))
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#define I3C_SLV_CCC_M (I3C_SLV_CCC_V << I3C_SLV_CCC_S)
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#define I3C_SLV_CCC_V 0x00000001U
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#define I3C_SLV_CCC_S 14
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/** I3C_SLV_ERRWARN : RO; bitpos: [15]; default: 0;
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* NA
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*/
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#define I3C_SLV_ERRWARN (BIT(15))
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#define I3C_SLV_ERRWARN_M (I3C_SLV_ERRWARN_V << I3C_SLV_ERRWARN_S)
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#define I3C_SLV_ERRWARN_V 0x00000001U
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#define I3C_SLV_ERRWARN_S 15
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/** I3C_SLV_HDRMATCH : R/W; bitpos: [16]; default: 0;
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* NA
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*/
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#define I3C_SLV_HDRMATCH (BIT(16))
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#define I3C_SLV_HDRMATCH_M (I3C_SLV_HDRMATCH_V << I3C_SLV_HDRMATCH_S)
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#define I3C_SLV_HDRMATCH_V 0x00000001U
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#define I3C_SLV_HDRMATCH_S 16
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/** I3C_SLV_CTRL_REG register
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* NA
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*/
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#define I3C_SLV_CTRL_REG (DR_REG_I3C_SLV_BASE + 0xc)
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/** I3C_SLV_SLV_EVENT : R/W; bitpos: [1:0]; default: 0;
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* If set to non-0, will request an event. Once requested, STATUS.EVENT and EVDET will
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* show the status as it progresses. Once completed, the field will automatically
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* return to 0. Once non-0, only 0 can be written(to cancel) until done. 0: Normal
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* mode. If set to 0 after was a non-0 value, will cancel if not already in flight. 1:
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* start an IBI. This will try to push through an IBI on the bus. If data associate
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* with the IBI, it will be drawn from the IBIDATA field. Note that if Time control is
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* enabled, this will include anytime control related bytes further, the IBIDATA byte
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* will have bit7 set to 1.
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*/
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#define I3C_SLV_SLV_EVENT 0x00000003U
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#define I3C_SLV_SLV_EVENT_M (I3C_SLV_SLV_EVENT_V << I3C_SLV_SLV_EVENT_S)
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#define I3C_SLV_SLV_EVENT_V 0x00000003U
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#define I3C_SLV_SLV_EVENT_S 0
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/** I3C_SLV_EXTDATA : R/W; bitpos: [3]; default: 0;
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* reserved
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*/
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#define I3C_SLV_EXTDATA (BIT(3))
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#define I3C_SLV_EXTDATA_M (I3C_SLV_EXTDATA_V << I3C_SLV_EXTDATA_S)
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#define I3C_SLV_EXTDATA_V 0x00000001U
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#define I3C_SLV_EXTDATA_S 3
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/** I3C_SLV_MAPIDX : R/W; bitpos: [7:4]; default: 0;
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* Index of Dynamic Address that IBI is for. This is 0 for the main or base Dynamic
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* Address, or can be any valid index.
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*/
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#define I3C_SLV_MAPIDX 0x0000000FU
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#define I3C_SLV_MAPIDX_M (I3C_SLV_MAPIDX_V << I3C_SLV_MAPIDX_S)
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#define I3C_SLV_MAPIDX_V 0x0000000FU
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#define I3C_SLV_MAPIDX_S 4
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/** I3C_SLV_IBIDATA : R/W; bitpos: [15:8]; default: 0;
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* Data byte to go with an IBI, if enabled for it. If enabled (was in BCR), then it is
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* required.
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*/
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#define I3C_SLV_IBIDATA 0x000000FFU
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#define I3C_SLV_IBIDATA_M (I3C_SLV_IBIDATA_V << I3C_SLV_IBIDATA_S)
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#define I3C_SLV_IBIDATA_V 0x000000FFU
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#define I3C_SLV_IBIDATA_S 8
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/** I3C_SLV_PENDINT : R/W; bitpos: [19:16]; default: 0;
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* Should be set to the pending interrupt that GETSTATUS CCC will return. This should
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* be maintained by the application if used and configured, as the Master will read
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* this. If not configured, the GETSTATUS field will return 1 if an IBI is pending,
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* and 0 otherwise.
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*/
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#define I3C_SLV_PENDINT 0x0000000FU
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#define I3C_SLV_PENDINT_M (I3C_SLV_PENDINT_V << I3C_SLV_PENDINT_S)
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#define I3C_SLV_PENDINT_V 0x0000000FU
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#define I3C_SLV_PENDINT_S 16
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/** I3C_SLV_ACTSTATE : R/W; bitpos: [21:20]; default: 0;
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* NA
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*/
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#define I3C_SLV_ACTSTATE 0x00000003U
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#define I3C_SLV_ACTSTATE_M (I3C_SLV_ACTSTATE_V << I3C_SLV_ACTSTATE_S)
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#define I3C_SLV_ACTSTATE_V 0x00000003U
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#define I3C_SLV_ACTSTATE_S 20
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/** I3C_SLV_VENDINFO : R/W; bitpos: [31:24]; default: 0;
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* NA
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*/
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#define I3C_SLV_VENDINFO 0x000000FFU
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#define I3C_SLV_VENDINFO_M (I3C_SLV_VENDINFO_V << I3C_SLV_VENDINFO_S)
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#define I3C_SLV_VENDINFO_V 0x000000FFU
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#define I3C_SLV_VENDINFO_S 24
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/** I3C_SLV_INTSET_REG register
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* INSET allows setting enables for interrupts(connecting the corresponding STATUS
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* source to causing an IRQ to the processor)
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*/
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#define I3C_SLV_INTSET_REG (DR_REG_I3C_SLV_BASE + 0x10)
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/** I3C_SLV_STOP_ENA : R/W; bitpos: [10]; default: 0;
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* Interrupt on STOP state on the bus. See Start as the preferred interrupt when
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* needed. This interrupt may not trigger for quick STOP/START combination, as it
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* relates to the state of being stopped.
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*/
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#define I3C_SLV_STOP_ENA (BIT(10))
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#define I3C_SLV_STOP_ENA_M (I3C_SLV_STOP_ENA_V << I3C_SLV_STOP_ENA_S)
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#define I3C_SLV_STOP_ENA_V 0x00000001U
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#define I3C_SLV_STOP_ENA_S 10
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/** I3C_SLV_RXPEND_ENA : R/W; bitpos: [11]; default: 0;
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* Interrupt when receiving a message from Master, which is not being handled by the
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* block (excludes CCCs being handled automatically). If FIFO, then RX fullness
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* trigger. If DMA, then message end.
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*/
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#define I3C_SLV_RXPEND_ENA (BIT(11))
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#define I3C_SLV_RXPEND_ENA_M (I3C_SLV_RXPEND_ENA_V << I3C_SLV_RXPEND_ENA_S)
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#define I3C_SLV_RXPEND_ENA_V 0x00000001U
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#define I3C_SLV_RXPEND_ENA_S 11
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/** I3C_SLV_TXSEND_ENA : R/W; bitpos: [12]; default: 0;
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* NA
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*/
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#define I3C_SLV_TXSEND_ENA (BIT(12))
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#define I3C_SLV_TXSEND_ENA_M (I3C_SLV_TXSEND_ENA_V << I3C_SLV_TXSEND_ENA_S)
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#define I3C_SLV_TXSEND_ENA_V 0x00000001U
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#define I3C_SLV_TXSEND_ENA_S 12
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/** I3C_SLV_INTCLR_REG register
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* NA
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*/
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#define I3C_SLV_INTCLR_REG (DR_REG_I3C_SLV_BASE + 0x14)
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/** I3C_SLV_STOP_CLR : WO; bitpos: [10]; default: 0;
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* Interrupt on STOP state on the bus. See Start as the preferred interrupt when
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* needed. This interrupt may not trigger for quick STOP/START combination, as it
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* relates to the state of being stopped.
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*/
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#define I3C_SLV_STOP_CLR (BIT(10))
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#define I3C_SLV_STOP_CLR_M (I3C_SLV_STOP_CLR_V << I3C_SLV_STOP_CLR_S)
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#define I3C_SLV_STOP_CLR_V 0x00000001U
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#define I3C_SLV_STOP_CLR_S 10
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/** I3C_SLV_RXPEND_CLR : WO; bitpos: [11]; default: 0;
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* Interrupt when receiving a message from Master, which is not being handled by the
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* block (excludes CCCs being handled automatically). If FIFO, then RX fullness
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* trigger. If DMA, then message end.
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*/
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#define I3C_SLV_RXPEND_CLR (BIT(11))
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#define I3C_SLV_RXPEND_CLR_M (I3C_SLV_RXPEND_CLR_V << I3C_SLV_RXPEND_CLR_S)
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#define I3C_SLV_RXPEND_CLR_V 0x00000001U
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#define I3C_SLV_RXPEND_CLR_S 11
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/** I3C_SLV_TXSEND_CLR : WO; bitpos: [12]; default: 0;
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* NA
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*/
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#define I3C_SLV_TXSEND_CLR (BIT(12))
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#define I3C_SLV_TXSEND_CLR_M (I3C_SLV_TXSEND_CLR_V << I3C_SLV_TXSEND_CLR_S)
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#define I3C_SLV_TXSEND_CLR_V 0x00000001U
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#define I3C_SLV_TXSEND_CLR_S 12
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/** I3C_SLV_INTMASKED_REG register
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* NA
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*/
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#define I3C_SLV_INTMASKED_REG (DR_REG_I3C_SLV_BASE + 0x18)
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/** I3C_SLV_STOP_MASK : RO; bitpos: [10]; default: 0;
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* Interrupt on STOP state on the bus. See Start as the preferred interrupt when
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* needed. This interrupt may not trigger for quick STOP/START combination, as it
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* relates to the state of being stopped.
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*/
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#define I3C_SLV_STOP_MASK (BIT(10))
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#define I3C_SLV_STOP_MASK_M (I3C_SLV_STOP_MASK_V << I3C_SLV_STOP_MASK_S)
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#define I3C_SLV_STOP_MASK_V 0x00000001U
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#define I3C_SLV_STOP_MASK_S 10
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/** I3C_SLV_RXPEND_MASK : RO; bitpos: [11]; default: 0;
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* Interrupt when receiving a message from Master, which is not being handled by the
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* block (excludes CCCs being handled automatically). If FIFO, then RX fullness
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* trigger. If DMA, then message end.
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*/
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#define I3C_SLV_RXPEND_MASK (BIT(11))
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#define I3C_SLV_RXPEND_MASK_M (I3C_SLV_RXPEND_MASK_V << I3C_SLV_RXPEND_MASK_S)
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#define I3C_SLV_RXPEND_MASK_V 0x00000001U
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#define I3C_SLV_RXPEND_MASK_S 11
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/** I3C_SLV_TXSEND_MASK : RO; bitpos: [12]; default: 0;
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* NA
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*/
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#define I3C_SLV_TXSEND_MASK (BIT(12))
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#define I3C_SLV_TXSEND_MASK_M (I3C_SLV_TXSEND_MASK_V << I3C_SLV_TXSEND_MASK_S)
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#define I3C_SLV_TXSEND_MASK_V 0x00000001U
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#define I3C_SLV_TXSEND_MASK_S 12
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/** I3C_SLV_DATACTRL_REG register
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* NA
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*/
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#define I3C_SLV_DATACTRL_REG (DR_REG_I3C_SLV_BASE + 0x2c)
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/** I3C_SLV_FLUSHTB : WO; bitpos: [0]; default: 0;
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* Flushes the from-bus buffer/FIFO. Not normally used
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*/
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#define I3C_SLV_FLUSHTB (BIT(0))
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#define I3C_SLV_FLUSHTB_M (I3C_SLV_FLUSHTB_V << I3C_SLV_FLUSHTB_S)
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#define I3C_SLV_FLUSHTB_V 0x00000001U
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#define I3C_SLV_FLUSHTB_S 0
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/** I3C_SLV_FLUSHFB : WO; bitpos: [1]; default: 0;
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* Flushes the to-bus buffer/FIFO. Used when Master terminates a to-bus (read) message
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* prematurely
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*/
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#define I3C_SLV_FLUSHFB (BIT(1))
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#define I3C_SLV_FLUSHFB_M (I3C_SLV_FLUSHFB_V << I3C_SLV_FLUSHFB_S)
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#define I3C_SLV_FLUSHFB_V 0x00000001U
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#define I3C_SLV_FLUSHFB_S 1
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/** I3C_SLV_UNLOCK : WO; bitpos: [3]; default: 0;
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* If this bit is not written 1, the register bits from 7 to 4 are not changed on
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* write.
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*/
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#define I3C_SLV_UNLOCK (BIT(3))
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#define I3C_SLV_UNLOCK_M (I3C_SLV_UNLOCK_V << I3C_SLV_UNLOCK_S)
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#define I3C_SLV_UNLOCK_V 0x00000001U
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#define I3C_SLV_UNLOCK_S 3
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/** I3C_SLV_TXTRIG : R/W; bitpos: [5:4]; default: 3;
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* Trigger level for tx emptiness when FIFOed, Affects interrupt and DMA(if enabled).
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* The defaults is 3
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*/
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#define I3C_SLV_TXTRIG 0x00000003U
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#define I3C_SLV_TXTRIG_M (I3C_SLV_TXTRIG_V << I3C_SLV_TXTRIG_S)
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#define I3C_SLV_TXTRIG_V 0x00000003U
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#define I3C_SLV_TXTRIG_S 4
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/** I3C_SLV_RXTRIG : R/W; bitpos: [7:6]; default: 2;
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* Trigger level for rx fulless when FIFOed, Affects interrupt and DMA(if enabled).
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* The defaults is 3
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*/
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#define I3C_SLV_RXTRIG 0x00000003U
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#define I3C_SLV_RXTRIG_M (I3C_SLV_RXTRIG_V << I3C_SLV_RXTRIG_S)
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#define I3C_SLV_RXTRIG_V 0x00000003U
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#define I3C_SLV_RXTRIG_S 6
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/** I3C_SLV_TXCOUNT : RO; bitpos: [20:16]; default: 0;
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* NA
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*/
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#define I3C_SLV_TXCOUNT 0x0000001FU
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#define I3C_SLV_TXCOUNT_M (I3C_SLV_TXCOUNT_V << I3C_SLV_TXCOUNT_S)
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#define I3C_SLV_TXCOUNT_V 0x0000001FU
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#define I3C_SLV_TXCOUNT_S 16
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/** I3C_SLV_RXCOUNT : RO; bitpos: [28:24]; default: 0;
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* NA
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*/
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#define I3C_SLV_RXCOUNT 0x0000001FU
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#define I3C_SLV_RXCOUNT_M (I3C_SLV_RXCOUNT_V << I3C_SLV_RXCOUNT_S)
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#define I3C_SLV_RXCOUNT_V 0x0000001FU
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#define I3C_SLV_RXCOUNT_S 24
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/** I3C_SLV_TXFULL : RO; bitpos: [30]; default: 0;
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* NA
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*/
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#define I3C_SLV_TXFULL (BIT(30))
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#define I3C_SLV_TXFULL_M (I3C_SLV_TXFULL_V << I3C_SLV_TXFULL_S)
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#define I3C_SLV_TXFULL_V 0x00000001U
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#define I3C_SLV_TXFULL_S 30
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/** I3C_SLV_RXEMPTY : RO; bitpos: [31]; default: 0;
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* NA
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*/
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#define I3C_SLV_RXEMPTY (BIT(31))
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#define I3C_SLV_RXEMPTY_M (I3C_SLV_RXEMPTY_V << I3C_SLV_RXEMPTY_S)
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#define I3C_SLV_RXEMPTY_V 0x00000001U
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#define I3C_SLV_RXEMPTY_S 31
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/** I3C_SLV_WDATAB_REG register
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* NA
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*/
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#define I3C_SLV_WDATAB_REG (DR_REG_I3C_SLV_BASE + 0x30)
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/** I3C_SLV_WDATAB : WO; bitpos: [7:0]; default: 0;
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* NA
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*/
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#define I3C_SLV_WDATAB 0x000000FFU
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#define I3C_SLV_WDATAB_M (I3C_SLV_WDATAB_V << I3C_SLV_WDATAB_S)
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#define I3C_SLV_WDATAB_V 0x000000FFU
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#define I3C_SLV_WDATAB_S 0
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/** I3C_SLV_WDATA_END : WO; bitpos: [8]; default: 0;
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* NA
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*/
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#define I3C_SLV_WDATA_END (BIT(8))
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#define I3C_SLV_WDATA_END_M (I3C_SLV_WDATA_END_V << I3C_SLV_WDATA_END_S)
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#define I3C_SLV_WDATA_END_V 0x00000001U
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#define I3C_SLV_WDATA_END_S 8
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/** I3C_SLV_WDATABE_REG register
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* NA
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*/
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#define I3C_SLV_WDATABE_REG (DR_REG_I3C_SLV_BASE + 0x34)
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/** I3C_SLV_WDATABE : WO; bitpos: [7:0]; default: 0;
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* NA
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*/
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#define I3C_SLV_WDATABE 0x000000FFU
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#define I3C_SLV_WDATABE_M (I3C_SLV_WDATABE_V << I3C_SLV_WDATABE_S)
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#define I3C_SLV_WDATABE_V 0x000000FFU
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#define I3C_SLV_WDATABE_S 0
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/** I3C_SLV_RDARAB_REG register
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* Read Byte Data (from-bus) register
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*/
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#define I3C_SLV_RDARAB_REG (DR_REG_I3C_SLV_BASE + 0x40)
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/** I3C_SLV_DATA0 : RO; bitpos: [7:0]; default: 0;
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* This register allows reading a byte from the bus unless external FIFO is used. A
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* byte should not be read unless there is data waiting, as indicated by the RXPEND
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* bit being set in the STATUS register
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*/
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#define I3C_SLV_DATA0 0x000000FFU
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#define I3C_SLV_DATA0_M (I3C_SLV_DATA0_V << I3C_SLV_DATA0_S)
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#define I3C_SLV_DATA0_V 0x000000FFU
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#define I3C_SLV_DATA0_S 0
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/** I3C_SLV_RDATAH_REG register
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* Read Half-word Data (from-bus) register
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*/
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#define I3C_SLV_RDATAH_REG (DR_REG_I3C_SLV_BASE + 0x48)
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/** I3C_SLV_DATA_LSB : RO; bitpos: [7:0]; default: 0;
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* NA
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*/
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#define I3C_SLV_DATA_LSB 0x000000FFU
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#define I3C_SLV_DATA_LSB_M (I3C_SLV_DATA_LSB_V << I3C_SLV_DATA_LSB_S)
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#define I3C_SLV_DATA_LSB_V 0x000000FFU
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#define I3C_SLV_DATA_LSB_S 0
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/** I3C_SLV_DATA_MSB : RO; bitpos: [15:8]; default: 0;
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* This register allows reading a Half-word (byte pair) from the bus unless external
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* FIFO is used. A Half-word should not be read unless there is at least 2 bytes of
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* data waiting, as indicated by the RX FIFO level trigger or RXCOUNT available space
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* in the DATACTRL register
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*/
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#define I3C_SLV_DATA_MSB 0x000000FFU
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#define I3C_SLV_DATA_MSB_M (I3C_SLV_DATA_MSB_V << I3C_SLV_DATA_MSB_S)
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#define I3C_SLV_DATA_MSB_V 0x000000FFU
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#define I3C_SLV_DATA_MSB_S 8
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/** I3C_SLV_CAPABILITIES2_REG register
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* NA
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*/
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#define I3C_SLV_CAPABILITIES2_REG (DR_REG_I3C_SLV_BASE + 0x5c)
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/** I3C_SLV_CAPABLITIES2 : RO; bitpos: [31:0]; default: 256;
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* NA
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*/
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#define I3C_SLV_CAPABLITIES2 0xFFFFFFFFU
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#define I3C_SLV_CAPABLITIES2_M (I3C_SLV_CAPABLITIES2_V << I3C_SLV_CAPABLITIES2_S)
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#define I3C_SLV_CAPABLITIES2_V 0xFFFFFFFFU
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#define I3C_SLV_CAPABLITIES2_S 0
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/** I3C_SLV_CAPABILITIES_REG register
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* NA
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*/
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#define I3C_SLV_CAPABILITIES_REG (DR_REG_I3C_SLV_BASE + 0x60)
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/** I3C_SLV_CAPABLITIES : RO; bitpos: [31:0]; default: 2081684508;
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* NA
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*/
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#define I3C_SLV_CAPABLITIES 0xFFFFFFFFU
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#define I3C_SLV_CAPABLITIES_M (I3C_SLV_CAPABLITIES_V << I3C_SLV_CAPABLITIES_S)
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#define I3C_SLV_CAPABLITIES_V 0xFFFFFFFFU
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#define I3C_SLV_CAPABLITIES_S 0
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/** I3C_SLV_IDPARTNO_REG register
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* NA
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*/
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#define I3C_SLV_IDPARTNO_REG (DR_REG_I3C_SLV_BASE + 0x6c)
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/** I3C_SLV_PARTNO : R/W; bitpos: [31:0]; default: 0;
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* NA
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*/
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#define I3C_SLV_PARTNO 0xFFFFFFFFU
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#define I3C_SLV_PARTNO_M (I3C_SLV_PARTNO_V << I3C_SLV_PARTNO_S)
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#define I3C_SLV_PARTNO_V 0xFFFFFFFFU
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#define I3C_SLV_PARTNO_S 0
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/** I3C_SLV_IDEXT_REG register
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* NA
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*/
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#define I3C_SLV_IDEXT_REG (DR_REG_I3C_SLV_BASE + 0x70)
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/** I3C_SLV_IDEXT : R/W; bitpos: [31:0]; default: 0;
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* NA
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*/
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#define I3C_SLV_IDEXT 0xFFFFFFFFU
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#define I3C_SLV_IDEXT_M (I3C_SLV_IDEXT_V << I3C_SLV_IDEXT_S)
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#define I3C_SLV_IDEXT_V 0xFFFFFFFFU
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#define I3C_SLV_IDEXT_S 0
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/** I3C_SLV_VENDORID_REG register
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* NA
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*/
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#define I3C_SLV_VENDORID_REG (DR_REG_I3C_SLV_BASE + 0x74)
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/** I3C_SLV_VID : R/W; bitpos: [14:0]; default: 21840;
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* NA
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*/
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#define I3C_SLV_VID 0x00007FFFU
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#define I3C_SLV_VID_M (I3C_SLV_VID_V << I3C_SLV_VID_S)
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#define I3C_SLV_VID_V 0x00007FFFU
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#define I3C_SLV_VID_S 0
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#ifdef __cplusplus
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}
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#endif
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