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https://github.com/espressif/esp-idf.git
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fa2707f1f3
If JTAG is disabled temporarily by burning SOFT_DIS_JTAG, it can be re-enabled temporarily through esp_hmac_jtag_enable API
188 lines
8.6 KiB
C
188 lines
8.6 KiB
C
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef __HWCRYPTO_REG_H__
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#define __HWCRYPTO_REG_H__
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#include "soc.h"
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/* registers for RSA acceleration via Multiple Precision Integer ops */
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#define RSA_MEM_M_BLOCK_BASE ((DR_REG_RSA_BASE)+0x000)
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/* RB & Z use the same memory block, depending on phase of operation */
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#define RSA_MEM_RB_BLOCK_BASE ((DR_REG_RSA_BASE)+0x200)
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#define RSA_MEM_Z_BLOCK_BASE ((DR_REG_RSA_BASE)+0x200)
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#define RSA_MEM_Y_BLOCK_BASE ((DR_REG_RSA_BASE)+0x400)
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#define RSA_MEM_X_BLOCK_BASE ((DR_REG_RSA_BASE)+0x600)
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/* Configuration registers */
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#define RSA_M_DASH_REG (DR_REG_RSA_BASE + 0x800)
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#define RSA_LENGTH_REG (DR_REG_RSA_BASE + 0x804)
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#define RSA_CONSTANT_TIME_REG (DR_REG_RSA_BASE + 0x820)
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#define RSA_SEARCH_ENABLE_REG (DR_REG_RSA_BASE + 0x824)
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#define RSA_SEARCH_POS_REG (DR_REG_RSA_BASE + 0x828)
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/* Initialization registers */
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#define RSA_QUERY_CLEAN_REG (DR_REG_RSA_BASE + 0x808)
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/* Calculation start registers */
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#define RSA_MODEXP_START_REG (DR_REG_RSA_BASE + 0x80c)
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#define RSA_MOD_MULT_START_REG (DR_REG_RSA_BASE + 0x810)
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#define RSA_MULT_START_REG (DR_REG_RSA_BASE + 0x814)
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/* Interrupt registers */
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#define RSA_QUERY_INTERRUPT_REG (DR_REG_RSA_BASE + 0x818)
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#define RSA_CLEAR_INTERRUPT_REG (DR_REG_RSA_BASE + 0x81C)
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#define RSA_INTERRUPT_REG (DR_REG_RSA_BASE + 0x82C)
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#define RSA_DATE_REG (DR_REG_RSA_BASE + 0x82C)
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#define SHA_MODE_SHA1 0
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#define SHA_MODE_SHA224 1
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#define SHA_MODE_SHA256 2
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/* SHA acceleration registers */
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#define SHA_MODE_REG ((DR_REG_SHA_BASE) + 0x00)
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#define SHA_BLOCK_NUM_REG ((DR_REG_SHA_BASE) + 0x0C)
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#define SHA_START_REG ((DR_REG_SHA_BASE) + 0x10)
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#define SHA_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x14)
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#define SHA_BUSY_REG ((DR_REG_SHA_BASE) + 0x18)
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#define SHA_DMA_START_REG ((DR_REG_SHA_BASE) + 0x1C)
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#define SHA_DMA_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x20)
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#define SHA_CLEAR_IRQ_REG ((DR_REG_SHA_BASE) + 0x24)
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#define SHA_INT_ENA_REG ((DR_REG_SHA_BASE) + 0x28)
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#define SHA_DATE_REG ((DR_REG_SHA_BASE) + 0x2C)
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#define SHA_H_BASE ((DR_REG_SHA_BASE) + 0x40)
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#define SHA_TEXT_BASE ((DR_REG_SHA_BASE) + 0x80)
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/* AES Block operation modes */
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#define AES_BLOCK_MODE_ECB 0
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#define AES_BLOCK_MODE_CBC 1
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#define AES_BLOCK_MODE_OFB 2
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#define AES_BLOCK_MODE_CTR 3
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#define AES_BLOCK_MODE_CFB8 4
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#define AES_BLOCK_MODE_CFB128 5
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/* AES Block operation modes (used with DMA) */
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#define AES_BLOCK_MODE_ECB 0
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#define AES_BLOCK_MODE_CBC 1
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#define AES_BLOCK_MODE_OFB 2
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#define AES_BLOCK_MODE_CTR 3
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#define AES_BLOCK_MODE_CFB8 4
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#define AES_BLOCK_MODE_CFB128 5
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/* AES acceleration registers */
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#define AES_MODE_REG ((DR_REG_AES_BASE) + 0x40)
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#define AES_ENDIAN_REG ((DR_REG_AES_BASE) + 0x44)
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#define AES_TRIGGER_REG ((DR_REG_AES_BASE) + 0x48)
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#define AES_STATE_REG ((DR_REG_AES_BASE) + 0x4c)
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#define AES_DMA_ENABLE_REG ((DR_REG_AES_BASE) + 0x90)
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#define AES_BLOCK_MODE_REG ((DR_REG_AES_BASE) + 0x94)
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#define AES_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0x98)
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#define AES_INC_SEL_REG ((DR_REG_AES_BASE) + 0x9C)
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#define AES_AAD_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0xA0)
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#define AES_BIT_VALID_NUM_REG ((DR_REG_AES_BASE) + 0xA4)
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#define AES_CONTINUE_REG ((DR_REG_AES_BASE) + 0xA8)
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#define AES_INT_CLEAR_REG ((DR_REG_AES_BASE) + 0xAC)
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#define AES_INT_ENA_REG ((DR_REG_AES_BASE) + 0xB0)
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#define AES_DATE_REG ((DR_REG_AES_BASE) + 0xB4)
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#define AES_DMA_EXIT_REG ((DR_REG_AES_BASE) + 0xB8)
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#define AES_DMA_ENABLE_REG ((DR_REG_AES_BASE) + 0x90)
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#define AES_BLOCK_MODE_REG ((DR_REG_AES_BASE) + 0x94)
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#define AES_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0x98)
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#define AES_INC_SEL_REG ((DR_REG_AES_BASE) + 0x9C)
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#define AES_AAD_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0xA0)
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#define AES_BIT_VALID_NUM_REG ((DR_REG_AES_BASE) + 0xA4)
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#define AES_CONTINUE_REG ((DR_REG_AES_BASE) + 0xA8)
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#define AES_KEY_BASE ((DR_REG_AES_BASE) + 0x00)
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#define AES_TEXT_IN_BASE ((DR_REG_AES_BASE) + 0x20)
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#define AES_TEXT_OUT_BASE ((DR_REG_AES_BASE) + 0x30)
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#define AES_IV_BASE ((DR_REG_AES_BASE) + 0x50)
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#define AES_H_BASE ((DR_REG_AES_BASE) + 0x60)
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#define AES_J_BASE ((DR_REG_AES_BASE) + 0x70)
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#define AES_T_BASE ((DR_REG_AES_BASE) + 0x80)
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#define AES_INT_CLR_REG ((DR_REG_AES_BASE) + 0xAC)
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#define AES_INT_ENA_REG ((DR_REG_AES_BASE) + 0xB0)
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#define AES_DATE_REG ((DR_REG_AES_BASE) + 0xB4)
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#define AES_DMA_EXIT_REG ((DR_REG_AES_BASE) + 0xB8)
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/* AES_STATE_REG values */
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#define AES_STATE_IDLE 0
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#define AES_STATE_BUSY 1
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#define AES_STATE_DONE 2
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/* HMAC Module */
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#define HMAC_SET_START_REG ((DR_REG_HMAC_BASE) + 0x40)
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#define HMAC_SET_PARA_PURPOSE_REG ((DR_REG_HMAC_BASE) + 0x44)
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#define HMAC_SET_PARA_KEY_REG ((DR_REG_HMAC_BASE) + 0x48)
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#define HMAC_SET_PARA_FINISH_REG ((DR_REG_HMAC_BASE) + 0x4c)
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#define HMAC_SET_MESSAGE_ONE_REG ((DR_REG_HMAC_BASE) + 0x50)
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#define HMAC_SET_MESSAGE_ING_REG ((DR_REG_HMAC_BASE) + 0x54)
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#define HMAC_SET_MESSAGE_END_REG ((DR_REG_HMAC_BASE) + 0x58)
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#define HMAC_SET_RESULT_FINISH_REG ((DR_REG_HMAC_BASE) + 0x5c)
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#define HMAC_SET_INVALIDATE_JTAG_REG ((DR_REG_HMAC_BASE) + 0x60)
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#define HMAC_INVALIDATE_JTAG BIT(0)
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#define HMAC_SET_INVALIDATE_DS_REG ((DR_REG_HMAC_BASE) + 0x64)
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#define HMAC_QUERY_ERROR_REG ((DR_REG_HMAC_BASE) + 0x68)
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#define HMAC_QUERY_BUSY_REG ((DR_REG_HMAC_BASE) + 0x6c)
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#define HMAC_WDATA_BASE ((DR_REG_HMAC_BASE) + 0x80)
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#define HMAC_RDATA_BASE ((DR_REG_HMAC_BASE) + 0xC0)
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#define HMAC_SET_MESSAGE_PAD_REG ((DR_REG_HMAC_BASE) + 0xF0)
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#define HMAC_ONE_BLOCK_REG ((DR_REG_HMAC_BASE) + 0xF4)
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#define HMAC_SOFT_JTAG_CTRL_REG ((DR_REG_HMAC_BASE) + 0xF8)
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#define HMAC_WR_JTAG_REG ((DR_REG_HMAC_BASE) + 0xFC)
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#define HMAC_DATE_REG ((DR_REG_HMAC_BASE) + 0xF8)
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/* AES-XTS registers */
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#define AES_XTS_PLAIN_BASE ((DR_REG_AES_XTS_BASE) + 0x00)
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#define AES_XTS_SIZE_REG ((DR_REG_AES_XTS_BASE) + 0x40)
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#define AES_XTS_DESTINATION_REG ((DR_REG_AES_XTS_BASE) + 0x44)
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#define AES_XTS_PHYSICAL_ADDR_REG ((DR_REG_AES_XTS_BASE) + 0x48)
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#define AES_XTS_TRIGGER_REG ((DR_REG_AES_XTS_BASE) + 0x4C)
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#define AES_XTS_RELEASE_REG ((DR_REG_AES_XTS_BASE) + 0x50)
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#define AES_XTS_DESTROY_REG ((DR_REG_AES_XTS_BASE) + 0x54)
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#define AES_XTS_STATE_REG ((DR_REG_AES_XTS_BASE) + 0x58)
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#define AES_XTS_DATE_REG ((DR_REG_AES_XTS_BASE) + 0x5C)
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/* Digital Signature registers and memory blocks */
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#define DS_C_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x000 )
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#define DS_C_Y_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x000 )
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#define DS_C_M_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x200 )
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#define DS_C_RB_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x400 )
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#define DS_C_BOX_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x600 )
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#define DS_IV_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x630 )
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#define DS_X_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x800 )
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#define DS_Z_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xA00 )
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#define DS_SET_START_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE00)
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#define DS_SET_ME_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE04)
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#define DS_SET_FINISH_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE08)
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#define DS_QUERY_BUSY_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE0C)
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#define DS_QUERY_KEY_WRONG_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE10)
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#define DS_QUERY_CHECK_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE14)
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#define DS_QUERY_CHECK_INVALID_DIGEST (1<<0)
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#define DS_QUERY_CHECK_INVALID_PADDING (1<<1)
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#define DS_DATE_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE20)
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#endif
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