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https://github.com/espressif/esp-idf.git
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647dea9395
During HAL layer refactoring and new chip bringup, we have several caps.h for each part, to reduce the conflicts to minimum. But this is The capabilities headers will be relataive stable once completely written (maybe after the featues are supported by drivers). Now ESP32 and ESP32-S2 drivers are relative stable, making it a good time to combine all these caps.h into one soc_caps.h This cleanup also move HAL config and pin config into separated files, to make the responsibilities of these headers more clear. This is helpful for the stabilities of soc_caps.h because we want to make it public some day.
86 lines
3.0 KiB
C
86 lines
3.0 KiB
C
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// The HAL layer for ADC (common part)
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#include "hal/adc_hal.h"
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#include "hal/adc_hal_conf.h"
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#include "hal/adc_types.h"
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void adc_hal_digi_init(void)
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{
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adc_hal_init();
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adc_ll_digi_set_clk_div(SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT);
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}
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void adc_hal_digi_deinit(void)
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{
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adc_ll_digi_clear_pattern_table(ADC_NUM_1);
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adc_ll_digi_clear_pattern_table(ADC_NUM_2);
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adc_hal_deinit();
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}
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void adc_hal_digi_controller_config(const adc_digi_config_t *cfg)
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{
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/* If enable digital controller, adc xpd should always on. */
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adc_ll_set_power_manage(ADC_POWER_SW_ON);
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/* Single channel mode or multi channel mode. */
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adc_ll_digi_set_convert_mode(cfg->conv_mode);
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if (cfg->conv_mode & ADC_CONV_SINGLE_UNIT_1) {
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adc_ll_set_controller(ADC_NUM_1, ADC_CTRL_DIG);
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if (cfg->adc1_pattern_len) {
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adc_ll_digi_clear_pattern_table(ADC_NUM_1);
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adc_ll_digi_set_pattern_table_len(ADC_NUM_1, cfg->adc1_pattern_len);
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for (int i = 0; i < cfg->adc1_pattern_len; i++) {
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adc_ll_digi_set_pattern_table(ADC_NUM_1, i, cfg->adc1_pattern[i]);
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}
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}
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}
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if (cfg->conv_mode & ADC_CONV_SINGLE_UNIT_2) {
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adc_ll_set_controller(ADC_NUM_2, ADC_CTRL_DIG);
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if (cfg->adc2_pattern_len) {
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adc_ll_digi_clear_pattern_table(ADC_NUM_2);
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adc_ll_digi_set_pattern_table_len(ADC_NUM_2, cfg->adc2_pattern_len);
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for (int i = 0; i < cfg->adc2_pattern_len; i++) {
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adc_ll_digi_set_pattern_table(ADC_NUM_2, i, cfg->adc2_pattern[i]);
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}
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}
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}
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adc_ll_digi_set_output_format(cfg->format);
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if (cfg->conv_limit_en) {
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adc_ll_digi_set_convert_limit_num(cfg->conv_limit_num);
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adc_ll_digi_convert_limit_enable();
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} else {
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adc_ll_digi_convert_limit_disable();
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}
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adc_ll_digi_set_data_source(ADC_I2S_DATA_SRC_ADC);
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}
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int adc_hal_hall_convert(void)
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{
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int Sens_Vp0;
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int Sens_Vn0;
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int Sens_Vp1;
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int Sens_Vn1;
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int hall_value;
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// convert for 4 times with different phase and outputs
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adc_ll_hall_phase_disable(); // hall phase
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adc_hal_convert( ADC_NUM_1, ADC_CHANNEL_0, &Sens_Vp0 );
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adc_hal_convert( ADC_NUM_1, ADC_CHANNEL_3, &Sens_Vn0 );
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adc_ll_hall_phase_enable();
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adc_hal_convert( ADC_NUM_1, ADC_CHANNEL_0, &Sens_Vp1 );
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adc_hal_convert( ADC_NUM_1, ADC_CHANNEL_3, &Sens_Vn1 );
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hall_value = (Sens_Vp1 - Sens_Vp0) - (Sens_Vn1 - Sens_Vn0);
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return hall_value;
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} |