mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
c19b37d2a9
In case when FRC and RTC counters are very different then the need to sync them before to restart the ESP to get the correct system time after reboot.
131 lines
3.5 KiB
C
131 lines
3.5 KiB
C
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
|
|
//
|
|
// Licensed under the Apache License, Version 2.0 (the "License");
|
|
// you may not use this file except in compliance with the License.
|
|
// You may obtain a copy of the License at
|
|
//
|
|
// http://www.apache.org/licenses/LICENSE-2.0
|
|
//
|
|
// Unless required by applicable law or agreed to in writing, software
|
|
// distributed under the License is distributed on an "AS IS" BASIS,
|
|
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
// See the License for the specific language governing permissions and
|
|
// limitations under the License.
|
|
|
|
#include "esp_system.h"
|
|
#include "esp_private/system_internal.h"
|
|
#include "esp_heap_caps.h"
|
|
#include "freertos/FreeRTOS.h"
|
|
#include "freertos/task.h"
|
|
#include "soc/cpu.h"
|
|
#include "soc/rtc.h"
|
|
#include "soc/rtc_cntl_reg.h"
|
|
#include "esp_private/panic_internal.h"
|
|
#include "esp_rom_uart.h"
|
|
#if CONFIG_IDF_TARGET_ESP32S2
|
|
#include "esp32s2/memprot.h"
|
|
#elif CONFIG_IDF_TARGET_ESP32S3
|
|
#include "esp32s3/memprot.h"
|
|
#elif CONFIG_IDF_TARGET_ESP32C3
|
|
#include "esp32c3/memprot.h"
|
|
#elif CONFIG_IDF_TARGET_ESP32H2
|
|
#include "esp32h2/memprot.h"
|
|
#endif
|
|
|
|
#define SHUTDOWN_HANDLERS_NO 5
|
|
|
|
static shutdown_handler_t shutdown_handlers[SHUTDOWN_HANDLERS_NO];
|
|
|
|
void IRAM_ATTR esp_restart_noos_dig(void)
|
|
{
|
|
// make sure all the panic handler output is sent from UART FIFO
|
|
if (CONFIG_ESP_CONSOLE_UART_NUM >= 0) {
|
|
esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
|
|
}
|
|
|
|
// switch to XTAL (otherwise we will keep running from the PLL)
|
|
rtc_clk_cpu_freq_set_xtal();
|
|
|
|
#if CONFIG_IDF_TARGET_ESP32
|
|
esp_cpu_unstall(PRO_CPU_NUM);
|
|
#endif
|
|
// reset the digital part
|
|
SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST);
|
|
while (true) {
|
|
;
|
|
}
|
|
}
|
|
|
|
esp_err_t esp_register_shutdown_handler(shutdown_handler_t handler)
|
|
{
|
|
for (int i = 0; i < SHUTDOWN_HANDLERS_NO; i++) {
|
|
if (shutdown_handlers[i] == handler) {
|
|
return ESP_ERR_INVALID_STATE;
|
|
} else if (shutdown_handlers[i] == NULL) {
|
|
shutdown_handlers[i] = handler;
|
|
return ESP_OK;
|
|
}
|
|
}
|
|
return ESP_ERR_NO_MEM;
|
|
}
|
|
|
|
esp_err_t esp_unregister_shutdown_handler(shutdown_handler_t handler)
|
|
{
|
|
for (int i = 0; i < SHUTDOWN_HANDLERS_NO; i++) {
|
|
if (shutdown_handlers[i] == handler) {
|
|
shutdown_handlers[i] = NULL;
|
|
return ESP_OK;
|
|
}
|
|
}
|
|
return ESP_ERR_INVALID_STATE;
|
|
}
|
|
|
|
|
|
void IRAM_ATTR esp_restart(void)
|
|
{
|
|
for (int i = SHUTDOWN_HANDLERS_NO - 1; i >= 0; i--) {
|
|
if (shutdown_handlers[i]) {
|
|
shutdown_handlers[i]();
|
|
}
|
|
}
|
|
|
|
// Disable scheduler on this core.
|
|
vTaskSuspendAll();
|
|
|
|
bool digital_reset_needed = false;
|
|
#if CONFIG_ESP_SYSTEM_CONFIG_MEMPROT_FEATURE
|
|
if (esp_memprot_is_intr_ena_any() || esp_memprot_is_locked_any()) {
|
|
digital_reset_needed = true;
|
|
}
|
|
#endif
|
|
if (digital_reset_needed) {
|
|
esp_restart_noos_dig();
|
|
}
|
|
esp_restart_noos();
|
|
}
|
|
|
|
uint32_t esp_get_free_heap_size( void )
|
|
{
|
|
return heap_caps_get_free_size( MALLOC_CAP_DEFAULT );
|
|
}
|
|
|
|
uint32_t esp_get_free_internal_heap_size( void )
|
|
{
|
|
return heap_caps_get_free_size( MALLOC_CAP_8BIT | MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL );
|
|
}
|
|
|
|
uint32_t esp_get_minimum_free_heap_size( void )
|
|
{
|
|
return heap_caps_get_minimum_free_size( MALLOC_CAP_DEFAULT );
|
|
}
|
|
|
|
const char *esp_get_idf_version(void)
|
|
{
|
|
return IDF_VER;
|
|
}
|
|
|
|
void __attribute__((noreturn)) esp_system_abort(const char *details)
|
|
{
|
|
panic_abort(details);
|
|
}
|