mirror of
https://github.com/espressif/esp-idf.git
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188 lines
4.1 KiB
C
188 lines
4.1 KiB
C
/**
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** Group: Configuration Register */
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/** Type of mode register
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* Initial configuration register.
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*/
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typedef union {
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struct {
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/** mode : R/W; bitpos: [2:0]; default: 0;
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* Sha mode.
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*/
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uint32_t mode:3;
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uint32_t reserved_3:29;
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};
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uint32_t val;
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} sha_mode_reg_t;
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/** Type of dma_block_num register
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* DMA configuration register 0.
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*/
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typedef union {
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struct {
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/** dma_block_num : R/W; bitpos: [5:0]; default: 0;
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* Dma-sha block number.
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*/
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uint32_t dma_block_num:6;
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uint32_t reserved_6:26;
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};
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uint32_t val;
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} sha_dma_block_num_reg_t;
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/** Type of start register
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* Typical SHA configuration register 0.
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*/
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typedef union {
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struct {
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uint32_t reserved_0:1;
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/** start : RO; bitpos: [31:1]; default: 0;
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* Reserved.
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*/
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uint32_t start:31;
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};
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uint32_t val;
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} sha_start_reg_t;
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/** Type of continue register
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* Typical SHA configuration register 1.
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*/
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typedef union {
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struct {
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uint32_t reserved_0:1;
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/** continue : RO; bitpos: [31:1]; default: 0;
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* Reserved.
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*/
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uint32_t conti:31;
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};
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uint32_t val;
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} sha_continue_reg_t;
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/** Type of dma_start register
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* DMA configuration register 1.
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*/
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typedef union {
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struct {
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/** dma_start : WO; bitpos: [0]; default: 0;
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* Start dma-sha.
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*/
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uint32_t dma_start:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} sha_dma_start_reg_t;
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/** Type of dma_continue register
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* DMA configuration register 2.
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*/
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typedef union {
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struct {
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/** dma_continue : WO; bitpos: [0]; default: 0;
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* Continue dma-sha.
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*/
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uint32_t dma_continue:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} sha_dma_continue_reg_t;
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/** Group: Status Register */
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/** Type of busy register
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* Busy register.
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*/
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typedef union {
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struct {
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/** busy_state : RO; bitpos: [0]; default: 0;
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* Sha busy state. 1'b0: idle. 1'b1: busy.
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*/
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uint32_t busy_state:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} sha_busy_reg_t;
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/** Group: Interrupt Register */
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/** Type of clear_irq register
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* Interrupt clear register.
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*/
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typedef union {
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struct {
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/** clear_interrupt : WO; bitpos: [0]; default: 0;
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* Clear sha interrupt.
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*/
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uint32_t clear_interrupt:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} sha_clear_irq_reg_t;
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/** Type of irq_ena register
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* Interrupt enable register.
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*/
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typedef union {
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struct {
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/** interrupt_ena : R/W; bitpos: [0]; default: 0;
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* Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable.
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*/
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uint32_t interrupt_ena:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} sha_irq_ena_reg_t;
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/** Group: Version Register */
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/** Type of date register
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* Date register.
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*/
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typedef union {
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struct {
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/** date : R/W; bitpos: [29:0]; default: 538972713;
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* Sha date information/ sha version information.
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*/
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uint32_t date:30;
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uint32_t reserved_30:2;
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};
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uint32_t val;
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} sha_date_reg_t;
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/** Group: memory type */
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typedef struct {
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volatile sha_mode_reg_t mode;
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uint32_t reserved_004[2];
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volatile sha_dma_block_num_reg_t dma_block_num;
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volatile sha_start_reg_t start;
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volatile sha_continue_reg_t conti;
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volatile sha_busy_reg_t busy;
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volatile sha_dma_start_reg_t dma_start;
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volatile sha_dma_continue_reg_t dma_continue;
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volatile sha_clear_irq_reg_t clear_irq;
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volatile sha_irq_ena_reg_t irq_ena;
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volatile sha_date_reg_t date;
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uint32_t reserved_030[4];
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volatile uint32_t h[16];
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volatile uint32_t m[16];
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} sha_dev_t;
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#ifndef __cplusplus
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_Static_assert(sizeof(sha_dev_t) == 0xc0, "Invalid size of sha_dev_t structure");
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#endif
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#ifdef __cplusplus
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}
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#endif
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