mirror of
https://github.com/espressif/esp-idf.git
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127 lines
5.3 KiB
C
127 lines
5.3 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define MODEM_CLKRST_CLK_CONF_REG (DR_REG_MODEM_CLKRST_BASE + 0x0)
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/* MODEM_CLKRST_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
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/*description: .*/
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#define MODEM_CLKRST_CLK_EN (BIT(0))
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#define MODEM_CLKRST_CLK_EN_M (BIT(0))
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#define MODEM_CLKRST_CLK_EN_V 0x1
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#define MODEM_CLKRST_CLK_EN_S 0
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#define MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG (DR_REG_MODEM_CLKRST_BASE + 0x4)
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/* MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM : R/W ;bitpos:[11:4] ;default: 8'h0 ; */
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/*description: .*/
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#define MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM 0x000000FF
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#define MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_M ((MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_V)<<(MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S))
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#define MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_V 0xFF
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#define MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S 4
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/* MODEM_CLKRST_LP_TIMER_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */
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/*description: .*/
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#define MODEM_CLKRST_LP_TIMER_SEL_XTAL32K (BIT(3))
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#define MODEM_CLKRST_LP_TIMER_SEL_XTAL32K_M (BIT(3))
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#define MODEM_CLKRST_LP_TIMER_SEL_XTAL32K_V 0x1
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#define MODEM_CLKRST_LP_TIMER_SEL_XTAL32K_S 3
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/* MODEM_CLKRST_LP_TIMER_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */
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/*description: .*/
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#define MODEM_CLKRST_LP_TIMER_SEL_XTAL (BIT(2))
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#define MODEM_CLKRST_LP_TIMER_SEL_XTAL_M (BIT(2))
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#define MODEM_CLKRST_LP_TIMER_SEL_XTAL_V 0x1
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#define MODEM_CLKRST_LP_TIMER_SEL_XTAL_S 2
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/* MODEM_CLKRST_LP_TIMER_SEL_8M : R/W ;bitpos:[1] ;default: 1'b0 ; */
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/*description: .*/
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#define MODEM_CLKRST_LP_TIMER_SEL_8M (BIT(1))
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#define MODEM_CLKRST_LP_TIMER_SEL_8M_M (BIT(1))
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#define MODEM_CLKRST_LP_TIMER_SEL_8M_V 0x1
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#define MODEM_CLKRST_LP_TIMER_SEL_8M_S 1
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/* MODEM_CLKRST_LP_TIMER_SEL_RTC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */
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/*description: .*/
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#define MODEM_CLKRST_LP_TIMER_SEL_RTC_SLOW (BIT(0))
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#define MODEM_CLKRST_LP_TIMER_SEL_RTC_SLOW_M (BIT(0))
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#define MODEM_CLKRST_LP_TIMER_SEL_RTC_SLOW_V 0x1
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#define MODEM_CLKRST_LP_TIMER_SEL_RTC_SLOW_S 0
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#define MODEM_CLKRST_COEX_LP_CLK_CONF_REG (DR_REG_MODEM_CLKRST_BASE + 0x8)
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/* MODEM_CLKRST_COEX_LPCLK_DIV_NUM : R/W ;bitpos:[11:4] ;default: 8'h0 ; */
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/*description: .*/
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#define MODEM_CLKRST_COEX_LPCLK_DIV_NUM 0x000000FF
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#define MODEM_CLKRST_COEX_LPCLK_DIV_NUM_M ((MODEM_CLKRST_COEX_LPCLK_DIV_NUM_V)<<(MODEM_CLKRST_COEX_LPCLK_DIV_NUM_S))
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#define MODEM_CLKRST_COEX_LPCLK_DIV_NUM_V 0xFF
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#define MODEM_CLKRST_COEX_LPCLK_DIV_NUM_S 4
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/* MODEM_CLKRST_COEX_LPCLK_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */
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/*description: .*/
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#define MODEM_CLKRST_COEX_LPCLK_SEL_XTAL32K (BIT(3))
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#define MODEM_CLKRST_COEX_LPCLK_SEL_XTAL32K_M (BIT(3))
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#define MODEM_CLKRST_COEX_LPCLK_SEL_XTAL32K_V 0x1
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#define MODEM_CLKRST_COEX_LPCLK_SEL_XTAL32K_S 3
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/* MODEM_CLKRST_COEX_LPCLK_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */
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/*description: .*/
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#define MODEM_CLKRST_COEX_LPCLK_SEL_XTAL (BIT(2))
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#define MODEM_CLKRST_COEX_LPCLK_SEL_XTAL_M (BIT(2))
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#define MODEM_CLKRST_COEX_LPCLK_SEL_XTAL_V 0x1
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#define MODEM_CLKRST_COEX_LPCLK_SEL_XTAL_S 2
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/* MODEM_CLKRST_COEX_LPCLK_SEL_8M : R/W ;bitpos:[1] ;default: 1'b0 ; */
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/*description: .*/
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#define MODEM_CLKRST_COEX_LPCLK_SEL_8M (BIT(1))
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#define MODEM_CLKRST_COEX_LPCLK_SEL_8M_M (BIT(1))
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#define MODEM_CLKRST_COEX_LPCLK_SEL_8M_V 0x1
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#define MODEM_CLKRST_COEX_LPCLK_SEL_8M_S 1
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/* MODEM_CLKRST_COEX_LPCLK_SEL_RTC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */
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/*description: .*/
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#define MODEM_CLKRST_COEX_LPCLK_SEL_RTC_SLOW (BIT(0))
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#define MODEM_CLKRST_COEX_LPCLK_SEL_RTC_SLOW_M (BIT(0))
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#define MODEM_CLKRST_COEX_LPCLK_SEL_RTC_SLOW_V 0x1
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#define MODEM_CLKRST_COEX_LPCLK_SEL_RTC_SLOW_S 0
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#define MODEM_CLKRST_BLE_TIMER_CLK_CONF_REG (DR_REG_MODEM_CLKRST_BASE + 0xC)
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/* MODEM_CLKRST_BLETIMER_CLK_IS_ACTIVE : R/W ;bitpos:[1] ;default: 1'b1 ; */
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/*description: .*/
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#define MODEM_CLKRST_BLETIMER_CLK_IS_ACTIVE (BIT(1))
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#define MODEM_CLKRST_BLETIMER_CLK_IS_ACTIVE_M (BIT(1))
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#define MODEM_CLKRST_BLETIMER_CLK_IS_ACTIVE_V 0x1
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#define MODEM_CLKRST_BLETIMER_CLK_IS_ACTIVE_S 1
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/* MODEM_CLKRST_BLETIMER_USE_XTAL : R/W ;bitpos:[0] ;default: 1'b1 ; */
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/*description: .*/
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#define MODEM_CLKRST_BLETIMER_USE_XTAL (BIT(0))
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#define MODEM_CLKRST_BLETIMER_USE_XTAL_M (BIT(0))
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#define MODEM_CLKRST_BLETIMER_USE_XTAL_V 0x1
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#define MODEM_CLKRST_BLETIMER_USE_XTAL_S 0
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#define MODEM_CLKRST_ETM_CLK_CONF_REG (DR_REG_MODEM_CLKRST_BASE + 0x10)
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/* MODEM_CLKRST_ETM_CLK_ACTIVE : R/W ;bitpos:[1] ;default: 1'b0 ; */
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/*description: .*/
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#define MODEM_CLKRST_ETM_CLK_ACTIVE (BIT(1))
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#define MODEM_CLKRST_ETM_CLK_ACTIVE_M (BIT(1))
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#define MODEM_CLKRST_ETM_CLK_ACTIVE_V 0x1
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#define MODEM_CLKRST_ETM_CLK_ACTIVE_S 1
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/* MODEM_CLKRST_ETM_CLK_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */
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/*description: .*/
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#define MODEM_CLKRST_ETM_CLK_SEL (BIT(0))
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#define MODEM_CLKRST_ETM_CLK_SEL_M (BIT(0))
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#define MODEM_CLKRST_ETM_CLK_SEL_V 0x1
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#define MODEM_CLKRST_ETM_CLK_SEL_S 0
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#define MODEM_CLKRST_DATE_REG (DR_REG_MODEM_CLKRST_BASE + 0xC)
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/* MODEM_CLKRST_DATE : R/W ;bitpos:[27:0] ;default: 28'h2107270 ; */
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/*description: .*/
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#define MODEM_CLKRST_DATE 0x0FFFFFFF
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#define MODEM_CLKRST_DATE_M ((MODEM_CLKRST_DATE_V)<<(MODEM_CLKRST_DATE_S))
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#define MODEM_CLKRST_DATE_V 0xFFFFFFF
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#define MODEM_CLKRST_DATE_S 0
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#ifdef __cplusplus
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}
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#endif
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