mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
edee3ee3cd
Closes: https://github.com/espressif/esp-idf/issues/9208 When I2S is configured into different modes, the slot sequence varies. This commit updates slot sequence tables and corresponding descriptions in (both code and programming guide).
462 lines
14 KiB
C
462 lines
14 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef volatile struct i2s_dev_s {
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uint32_t fifo_wr;
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uint32_t fifo_rd;
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union {
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struct {
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uint32_t tx_reset: 1;
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uint32_t rx_reset: 1;
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uint32_t tx_fifo_reset: 1;
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uint32_t rx_fifo_reset: 1;
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uint32_t tx_start: 1;
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uint32_t rx_start: 1;
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uint32_t tx_slave_mod: 1;
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uint32_t rx_slave_mod: 1;
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uint32_t tx_right_first: 1;
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uint32_t rx_right_first: 1;
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uint32_t tx_msb_shift: 1;
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uint32_t rx_msb_shift: 1;
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uint32_t tx_short_sync: 1;
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uint32_t rx_short_sync: 1;
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uint32_t tx_mono: 1;
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uint32_t rx_mono: 1;
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uint32_t tx_msb_right: 1;
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uint32_t rx_msb_right: 1;
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uint32_t sig_loopback: 1;
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uint32_t reserved19: 13;
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};
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uint32_t val;
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} conf;
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union {
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struct {
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uint32_t rx_take_data: 1;
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uint32_t tx_put_data: 1;
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uint32_t rx_wfull: 1;
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uint32_t rx_rempty: 1;
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uint32_t tx_wfull: 1;
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uint32_t tx_rempty: 1;
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uint32_t rx_hung: 1;
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uint32_t tx_hung: 1;
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uint32_t in_done: 1;
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uint32_t in_suc_eof: 1;
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uint32_t in_err_eof: 1;
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uint32_t out_done: 1;
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uint32_t out_eof: 1;
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uint32_t in_dscr_err: 1;
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uint32_t out_dscr_err: 1;
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uint32_t in_dscr_empty: 1;
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uint32_t out_total_eof: 1;
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uint32_t reserved17: 15;
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};
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uint32_t val;
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} int_raw;
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union {
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struct {
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uint32_t rx_take_data: 1;
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uint32_t tx_put_data: 1;
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uint32_t rx_wfull: 1;
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uint32_t rx_rempty: 1;
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uint32_t tx_wfull: 1;
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uint32_t tx_rempty: 1;
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uint32_t rx_hung: 1;
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uint32_t tx_hung: 1;
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uint32_t in_done: 1;
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uint32_t in_suc_eof: 1;
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uint32_t in_err_eof: 1;
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uint32_t out_done: 1;
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uint32_t out_eof: 1;
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uint32_t in_dscr_err: 1;
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uint32_t out_dscr_err: 1;
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uint32_t in_dscr_empty: 1;
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uint32_t out_total_eof: 1;
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uint32_t reserved17: 15;
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};
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uint32_t val;
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} int_st;
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union {
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struct {
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uint32_t rx_take_data: 1;
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uint32_t tx_put_data: 1;
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uint32_t rx_wfull: 1;
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uint32_t rx_rempty: 1;
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uint32_t tx_wfull: 1;
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uint32_t tx_rempty: 1;
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uint32_t rx_hung: 1;
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uint32_t tx_hung: 1;
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uint32_t in_done: 1;
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uint32_t in_suc_eof: 1;
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uint32_t in_err_eof: 1;
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uint32_t out_done: 1;
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uint32_t out_eof: 1;
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uint32_t in_dscr_err: 1;
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uint32_t out_dscr_err: 1;
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uint32_t in_dscr_empty: 1;
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uint32_t out_total_eof: 1;
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uint32_t reserved17: 15;
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};
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uint32_t val;
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} int_ena;
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union {
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struct {
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uint32_t take_data: 1;
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uint32_t put_data: 1;
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uint32_t rx_wfull: 1;
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uint32_t rx_rempty: 1;
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uint32_t tx_wfull: 1;
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uint32_t tx_rempty: 1;
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uint32_t rx_hung: 1;
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uint32_t tx_hung: 1;
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uint32_t in_done: 1;
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uint32_t in_suc_eof: 1;
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uint32_t in_err_eof: 1;
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uint32_t out_done: 1;
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uint32_t out_eof: 1;
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uint32_t in_dscr_err: 1;
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uint32_t out_dscr_err: 1;
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uint32_t in_dscr_empty: 1;
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uint32_t out_total_eof: 1;
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uint32_t reserved17: 15;
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};
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uint32_t val;
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} int_clr;
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union {
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struct {
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uint32_t tx_bck_in_delay: 2;
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uint32_t tx_ws_in_delay: 2;
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uint32_t rx_bck_in_delay: 2;
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uint32_t rx_ws_in_delay: 2;
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uint32_t rx_sd_in_delay: 2;
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uint32_t tx_bck_out_delay: 2;
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uint32_t tx_ws_out_delay: 2;
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uint32_t tx_sd_out_delay: 2;
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uint32_t rx_ws_out_delay: 2;
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uint32_t rx_bck_out_delay: 2;
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uint32_t tx_dsync_sw: 1;
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uint32_t rx_dsync_sw: 1;
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uint32_t data_enable_delay: 2;
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uint32_t tx_bck_in_inv: 1;
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uint32_t reserved25: 7;
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};
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uint32_t val;
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} timing;
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union {
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struct {
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uint32_t rx_data_num: 6;
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uint32_t tx_data_num: 6;
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uint32_t dscr_en: 1;
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uint32_t tx_fifo_mod: 3;
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uint32_t rx_fifo_mod: 3;
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uint32_t tx_fifo_mod_force_en: 1;
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uint32_t rx_fifo_mod_force_en: 1;
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uint32_t reserved21: 11;
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};
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uint32_t val;
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} fifo_conf;
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uint32_t rx_eof_num;
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uint32_t conf_single_data;
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union {
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struct {
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uint32_t tx_chan_mod: 3;
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uint32_t rx_chan_mod: 2;
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uint32_t reserved5: 27;
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};
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uint32_t val;
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} conf_chan;
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union {
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struct {
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uint32_t addr: 20;
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uint32_t reserved20: 8;
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uint32_t stop: 1;
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uint32_t start: 1;
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uint32_t restart: 1;
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uint32_t park: 1;
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};
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uint32_t val;
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} out_link;
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union {
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struct {
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uint32_t addr: 20;
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uint32_t reserved20: 8;
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uint32_t stop: 1;
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uint32_t start: 1;
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uint32_t restart: 1;
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uint32_t park: 1;
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};
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uint32_t val;
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} in_link;
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uint32_t out_eof_des_addr;
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uint32_t in_eof_des_addr;
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uint32_t out_eof_bfr_des_addr;
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union {
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struct {
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uint32_t mode: 3;
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uint32_t reserved3: 1;
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uint32_t addr: 2;
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uint32_t reserved6: 26;
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};
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uint32_t val;
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} ahb_test;
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uint32_t in_link_dscr;
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uint32_t in_link_dscr_bf0;
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uint32_t in_link_dscr_bf1;
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uint32_t out_link_dscr;
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uint32_t out_link_dscr_bf0;
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uint32_t out_link_dscr_bf1;
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union {
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struct {
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uint32_t in_rst: 1;
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uint32_t out_rst: 1;
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uint32_t ahbm_fifo_rst: 1;
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uint32_t ahbm_rst: 1;
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uint32_t out_loop_test: 1;
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uint32_t in_loop_test: 1;
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uint32_t out_auto_wrback: 1;
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uint32_t out_no_restart_clr: 1;
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uint32_t out_eof_mode: 1;
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uint32_t outdscr_burst_en: 1;
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uint32_t indscr_burst_en: 1;
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uint32_t out_data_burst_en: 1;
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uint32_t check_owner: 1;
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uint32_t mem_trans_en: 1;
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uint32_t reserved14: 18;
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};
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uint32_t val;
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} lc_conf;
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union {
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struct {
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uint32_t wdata: 9;
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uint32_t reserved9: 7;
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uint32_t push: 1;
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uint32_t reserved17: 15;
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};
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uint32_t val;
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} out_fifo_push;
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union {
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struct {
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uint32_t rdata: 12;
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uint32_t reserved12: 4;
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uint32_t pop: 1;
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uint32_t reserved17: 15;
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};
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uint32_t val;
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} in_fifo_pop;
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uint32_t lc_state0;
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uint32_t lc_state1;
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union {
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struct {
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uint32_t fifo_timeout: 8;
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uint32_t fifo_timeout_shift: 3;
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uint32_t fifo_timeout_ena: 1;
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uint32_t reserved12: 20;
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};
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uint32_t val;
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} lc_hung_conf;
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uint32_t reserved_78;
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uint32_t reserved_7c;
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union {
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struct {
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uint32_t y_max:16;
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uint32_t y_min:16;
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};
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uint32_t val;
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} cvsd_conf0;
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union {
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struct {
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uint32_t sigma_max:16;
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uint32_t sigma_min:16;
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};
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uint32_t val;
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} cvsd_conf1;
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union {
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struct {
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uint32_t cvsd_k: 3;
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uint32_t cvsd_j: 3;
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uint32_t cvsd_beta: 10;
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uint32_t cvsd_h: 3;
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uint32_t reserved19:13;
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};
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uint32_t val;
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} cvsd_conf2;
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union {
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struct {
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uint32_t good_pack_max: 6;
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uint32_t n_err_seg: 3;
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uint32_t shift_rate: 3;
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uint32_t max_slide_sample: 8;
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uint32_t pack_len_8k: 5;
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uint32_t n_min_err: 3;
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uint32_t reserved28: 4;
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};
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uint32_t val;
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} plc_conf0;
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union {
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struct {
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uint32_t bad_cef_atten_para: 8;
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uint32_t bad_cef_atten_para_shift: 4;
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uint32_t bad_ola_win2_para_shift: 4;
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uint32_t bad_ola_win2_para: 8;
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uint32_t slide_win_len: 8;
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};
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uint32_t val;
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} plc_conf1;
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union {
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struct {
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uint32_t cvsd_seg_mod: 2;
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uint32_t min_period: 5;
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uint32_t reserved7: 25;
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};
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uint32_t val;
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} plc_conf2;
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union {
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struct {
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uint32_t en: 1;
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uint32_t chan_mod: 1;
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uint32_t cvsd_dec_pack_err: 1;
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uint32_t cvsd_pack_len_8k: 5;
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uint32_t cvsd_inf_en: 1;
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uint32_t cvsd_dec_start: 1;
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uint32_t cvsd_dec_reset: 1;
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uint32_t plc_en: 1;
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uint32_t plc2dma_en: 1;
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uint32_t reserved13: 19;
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};
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uint32_t val;
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} esco_conf0;
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union {
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struct {
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uint32_t with_en: 1;
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uint32_t no_en: 1;
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uint32_t cvsd_enc_start: 1;
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uint32_t cvsd_enc_reset: 1;
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uint32_t reserved4: 28;
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};
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uint32_t val;
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} sco_conf0;
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union {
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struct {
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uint32_t tx_pcm_conf: 3;
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uint32_t tx_pcm_bypass: 1;
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uint32_t rx_pcm_conf: 3;
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uint32_t rx_pcm_bypass: 1;
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uint32_t tx_stop_en: 1;
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uint32_t tx_zeros_rm_en: 1;
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uint32_t reserved10: 22;
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};
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uint32_t val;
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} conf1;
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union {
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struct {
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uint32_t fifo_force_pd: 1;
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uint32_t fifo_force_pu: 1;
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uint32_t plc_mem_force_pd: 1;
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uint32_t plc_mem_force_pu: 1;
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uint32_t reserved4: 28;
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};
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uint32_t val;
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} pd_conf;
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union {
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struct {
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uint32_t camera_en: 1;
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uint32_t lcd_tx_wrx2_en: 1;
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uint32_t lcd_tx_sdx2_en: 1;
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uint32_t data_enable_test_en: 1;
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uint32_t data_enable: 1;
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uint32_t lcd_en: 1;
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uint32_t ext_adc_start_en: 1;
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uint32_t inter_valid_en: 1;
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uint32_t reserved8: 24;
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};
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uint32_t val;
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} conf2;
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union {
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struct {
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uint32_t clkm_div_num: 8;
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uint32_t clkm_div_b: 6;
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uint32_t clkm_div_a: 6;
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uint32_t clk_en: 1;
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uint32_t clka_en: 1;
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uint32_t reserved22: 10;
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};
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uint32_t val;
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} clkm_conf;
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union {
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struct {
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uint32_t tx_bck_div_num: 6;
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uint32_t rx_bck_div_num: 6;
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uint32_t tx_bits_mod: 6;
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uint32_t rx_bits_mod: 6;
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uint32_t reserved24: 8;
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};
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uint32_t val;
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} sample_rate_conf;
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union {
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struct {
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uint32_t tx_pdm_en: 1;
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uint32_t rx_pdm_en: 1;
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uint32_t pcm2pdm_conv_en: 1;
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uint32_t pdm2pcm_conv_en: 1;
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uint32_t tx_sinc_osr2: 4;
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uint32_t tx_prescale: 8;
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uint32_t tx_hp_in_shift: 2;
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uint32_t tx_lp_in_shift: 2;
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uint32_t tx_sinc_in_shift: 2;
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uint32_t tx_sigmadelta_in_shift: 2;
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uint32_t rx_sinc_dsr_16_en: 1;
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uint32_t txhp_bypass: 1;
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uint32_t reserved26: 6;
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};
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uint32_t val;
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} pdm_conf;
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union {
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struct {
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uint32_t tx_pdm_fs: 10;
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uint32_t tx_pdm_fp: 10;
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uint32_t reserved20:12;
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};
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uint32_t val;
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} pdm_freq_conf;
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union {
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struct {
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uint32_t tx_idle: 1;
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uint32_t tx_fifo_reset_back: 1;
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uint32_t rx_fifo_reset_back: 1;
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uint32_t reserved3: 29;
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};
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uint32_t val;
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} state;
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uint32_t reserved_c0;
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uint32_t reserved_c4;
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uint32_t reserved_c8;
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uint32_t reserved_cc;
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uint32_t reserved_d0;
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uint32_t reserved_d4;
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uint32_t reserved_d8;
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uint32_t reserved_dc;
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uint32_t reserved_e0;
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uint32_t reserved_e4;
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uint32_t reserved_e8;
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uint32_t reserved_ec;
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uint32_t reserved_f0;
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uint32_t reserved_f4;
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uint32_t reserved_f8;
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uint32_t date; /**/
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} i2s_dev_t;
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extern i2s_dev_t I2S0;
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extern i2s_dev_t I2S1;
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#ifdef __cplusplus
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}
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#endif
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