mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
cf93777077
Deprecated rtc_xtal_freq_t, replaced with soc_xtal_freq_t defined in clk_tree_defs.h in soc component.
185 lines
6.5 KiB
C
185 lines
6.5 KiB
C
/*
|
|
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
#pragma once
|
|
|
|
#include "soc/soc.h"
|
|
#include "soc/rtc_cntl_reg.h"
|
|
#include "soc/syscon_reg.h"
|
|
#include "esp_attr.h"
|
|
#include "hal/assert.h"
|
|
|
|
#ifdef __cplusplus
|
|
extern "C" {
|
|
#endif
|
|
|
|
#define RTC_CNTL_LL_RETENTION_TARGET_CPU (BIT(0))
|
|
#define RTC_CNTL_LL_RETENTION_TARGET_TAGMEM (BIT(1))
|
|
|
|
FORCE_INLINE_ATTR void rtc_cntl_ll_set_wakeup_timer(uint64_t t)
|
|
{
|
|
WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX);
|
|
WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32);
|
|
|
|
SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, RTC_CNTL_MAIN_TIMER_INT_CLR_M);
|
|
SET_PERI_REG_MASK(RTC_CNTL_SLP_TIMER1_REG, RTC_CNTL_MAIN_TIMER_ALARM_EN_M);
|
|
}
|
|
|
|
FORCE_INLINE_ATTR void rtc_cntl_ll_ext1_clear_wakeup_status(void)
|
|
{
|
|
REG_SET_BIT(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_STATUS_CLR);
|
|
}
|
|
|
|
FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_ext1_get_wakeup_status(void)
|
|
{
|
|
return REG_GET_FIELD(RTC_CNTL_EXT_WAKEUP1_STATUS_REG, RTC_CNTL_EXT_WAKEUP1_STATUS);
|
|
}
|
|
|
|
FORCE_INLINE_ATTR void rtc_cntl_ll_ext1_set_wakeup_pins(uint32_t io_mask, uint32_t mode_mask)
|
|
{
|
|
// The target only supports a unified trigger mode among all EXT1 wakeup IOs
|
|
HAL_ASSERT((io_mask & mode_mask) == io_mask || (io_mask & mode_mask) == 0);
|
|
REG_SET_FIELD(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL, io_mask);
|
|
if ((io_mask & mode_mask) == io_mask) {
|
|
SET_PERI_REG_BITS(RTC_CNTL_EXT_WAKEUP_CONF_REG, 0x1,
|
|
1, RTC_CNTL_EXT_WAKEUP1_LV_S);
|
|
} else {
|
|
SET_PERI_REG_BITS(RTC_CNTL_EXT_WAKEUP_CONF_REG, 0x1,
|
|
0, RTC_CNTL_EXT_WAKEUP1_LV_S);
|
|
}
|
|
}
|
|
|
|
FORCE_INLINE_ATTR void rtc_cntl_ll_ext1_clear_wakeup_pins(void)
|
|
{
|
|
CLEAR_PERI_REG_MASK(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL_M);
|
|
}
|
|
|
|
FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_ext1_get_wakeup_pins(void)
|
|
{
|
|
return REG_GET_FIELD(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL);
|
|
}
|
|
|
|
FORCE_INLINE_ATTR void rtc_cntl_ll_set_tagmem_retention_link_addr(uint32_t link_addr)
|
|
{
|
|
REG_SET_FIELD(SYSCON_RETENTION_CTRL1_REG, SYSCON_RETENTION_TAG_LINK_ADDR, link_addr);
|
|
}
|
|
|
|
FORCE_INLINE_ATTR void rtc_cntl_ll_enable_tagmem_retention(void)
|
|
{
|
|
/* Enable i/d-cache tagmem retenttion. cpu: 1, tagmem: 2, cpu + tagmem: 3 */
|
|
uint32_t target = REG_GET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_TARGET);
|
|
REG_SET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_TARGET, (target | RTC_CNTL_LL_RETENTION_TARGET_TAGMEM));
|
|
}
|
|
|
|
FORCE_INLINE_ATTR void rtc_cntl_ll_enable_icache_tagmem_retention(uint32_t start_point, uint32_t vld_size, uint32_t size)
|
|
{
|
|
REG_SET_FIELD(SYSCON_RETENTION_CTRL2_REG, SYSCON_RET_ICACHE_START_POINT, start_point);
|
|
REG_SET_FIELD(SYSCON_RETENTION_CTRL2_REG, SYSCON_RET_ICACHE_VLD_SIZE, vld_size);
|
|
REG_SET_FIELD(SYSCON_RETENTION_CTRL2_REG, SYSCON_RET_ICACHE_SIZE, size);
|
|
REG_SET_BIT(SYSCON_RETENTION_CTRL2_REG, SYSCON_RET_ICACHE_ENABLE);
|
|
}
|
|
|
|
FORCE_INLINE_ATTR void rtc_cntl_ll_enable_dcache_tagmem_retention(uint32_t start_point, uint32_t vld_size, uint32_t size)
|
|
{
|
|
REG_SET_FIELD(SYSCON_RETENTION_CTRL3_REG, SYSCON_RET_DCACHE_START_POINT, start_point);
|
|
REG_SET_FIELD(SYSCON_RETENTION_CTRL3_REG, SYSCON_RET_DCACHE_VLD_SIZE, vld_size);
|
|
REG_SET_FIELD(SYSCON_RETENTION_CTRL3_REG, SYSCON_RET_DCACHE_SIZE, size);
|
|
REG_SET_BIT(SYSCON_RETENTION_CTRL3_REG, SYSCON_RET_DCACHE_ENABLE);
|
|
}
|
|
|
|
FORCE_INLINE_ATTR void rtc_cntl_ll_disable_tagmem_retention(void)
|
|
{
|
|
/* Enable i/d-cache tagmem retenttion. cpu: 1, tagmem: 2, cpu + tagmem: 3 */
|
|
uint32_t target = REG_GET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_TARGET);
|
|
REG_SET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_TARGET, (target & ~RTC_CNTL_LL_RETENTION_TARGET_TAGMEM));
|
|
}
|
|
|
|
FORCE_INLINE_ATTR void rtc_cntl_ll_disable_icache_tagmem_retention(void)
|
|
{
|
|
REG_CLR_BIT(SYSCON_RETENTION_CTRL2_REG, SYSCON_RET_ICACHE_ENABLE);
|
|
}
|
|
|
|
FORCE_INLINE_ATTR void rtc_cntl_ll_disable_dcache_tagmem_retention(void)
|
|
{
|
|
REG_CLR_BIT(SYSCON_RETENTION_CTRL3_REG, SYSCON_RET_DCACHE_ENABLE);
|
|
}
|
|
|
|
FORCE_INLINE_ATTR void rtc_cntl_ll_set_cpu_retention_link_addr(uint32_t link_addr)
|
|
{
|
|
REG_SET_FIELD(SYSCON_RETENTION_CTRL_REG, SYSCON_RETENTION_CPU_LINK_ADDR, link_addr);
|
|
}
|
|
|
|
FORCE_INLINE_ATTR void rtc_cntl_ll_enable_cpu_retention_clock(void)
|
|
{
|
|
REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN); /* Enable internal 20 MHz clock */
|
|
}
|
|
|
|
FORCE_INLINE_ATTR void rtc_cntl_ll_enable_cpu_retention(void)
|
|
{
|
|
uint32_t target = REG_GET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_TARGET);
|
|
|
|
REG_SET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_TARGET, (target | RTC_CNTL_LL_RETENTION_TARGET_CPU));
|
|
/* Enable retention when cpu sleep enable */
|
|
REG_SET_BIT(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_EN);
|
|
}
|
|
|
|
FORCE_INLINE_ATTR void rtc_cntl_ll_config_cpu_retention_timing(int wait, int clkoff_wait, int done_wait)
|
|
{
|
|
REG_SET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_WAIT, wait);
|
|
REG_SET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_CLKOFF_WAIT, clkoff_wait);
|
|
REG_SET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_DONE_WAIT, done_wait);
|
|
}
|
|
|
|
FORCE_INLINE_ATTR void rtc_cntl_ll_disable_cpu_retention(void)
|
|
{
|
|
REG_CLR_BIT(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_EN);
|
|
}
|
|
|
|
FORCE_INLINE_ATTR void rtc_cntl_ll_ulp_int_clear(void)
|
|
{
|
|
REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_ULP_CP_INT_CLR);
|
|
REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_COCPU_INT_CLR);
|
|
REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_COCPU_TRAP_INT_CLR);
|
|
}
|
|
|
|
FORCE_INLINE_ATTR void rtc_cntl_ll_timer2_set_touch_wait_cycle(uint32_t wait_cycle)
|
|
{
|
|
REG_SET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT, wait_cycle);
|
|
}
|
|
|
|
FORCE_INLINE_ATTR void rtc_cntl_ll_reset_system(void)
|
|
{
|
|
REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST);
|
|
}
|
|
|
|
FORCE_INLINE_ATTR void rtc_cntl_ll_reset_cpu(int cpu_no)
|
|
{
|
|
uint32_t rtc_cntl_rst = (cpu_no == 0) ? RTC_CNTL_SW_PROCPU_RST : RTC_CNTL_SW_APPCPU_RST;
|
|
REG_WRITE(RTC_CNTL_OPTIONS0_REG, rtc_cntl_rst);
|
|
}
|
|
|
|
FORCE_INLINE_ATTR void rtc_cntl_ll_sleep_enable(void)
|
|
{
|
|
SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN);
|
|
}
|
|
|
|
FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_get_rtc_time(void)
|
|
{
|
|
SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE);
|
|
uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG);
|
|
t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32;
|
|
return t;
|
|
}
|
|
|
|
FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_get_wakeup_cause(void)
|
|
{
|
|
return REG_GET_FIELD(RTC_CNTL_SLP_WAKEUP_CAUSE_REG, RTC_CNTL_WAKEUP_CAUSE);
|
|
}
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|