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https://github.com/espressif/esp-idf.git
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177 lines
7.1 KiB
C
177 lines
7.1 KiB
C
/*
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* SPDX-FileCopyrightText: 2010-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#ifndef CONFIG_IDF_TARGET_ESP32S2
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#error This file should only be included for ESP32-S2 target
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#endif
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#include <stdint.h>
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#include <stdbool.h>
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#include "esp_attr.h"
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#include "soc/spi_mem_reg.h"
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#include "esp_rom_spiflash.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*************************************************************
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* Note
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*************************************************************
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* 1. ESP32 chip have 4 SPI slave/master, however, SPI0 is
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* used as an SPI master to access Flash and ext-SRAM by
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* Cache module. It will support Decryto read for Flash,
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* read/write for ext-SRAM. And SPI1 is also used as an
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* SPI master for Flash read/write and ext-SRAM read/write.
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* It will support Encrypto write for Flash.
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* 2. As an SPI master, SPI support Highest clock to 80M,
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* however, Flash with 80M Clock should be configured
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* for different Flash chips. If you want to use 80M
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* clock We should use the SPI that is certified by
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* Espressif. However, the certification is not started
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* at the time, so please use 40M clock at the moment.
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* 3. SPI Flash can use 2 lines or 4 lines mode. If you
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* use 2 lines mode, you can save two pad SPIHD and
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* SPIWP for gpio. ESP32 support configured SPI pad for
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* Flash, the configuration is stored in efuse and flash.
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* However, the configurations of pads should be certified
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* by Espressif. If you use this function, please use 40M
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* clock at the moment.
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* 4. ESP32 support to use Common SPI command to configure
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* Flash to QIO mode, if you failed to configure with fix
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* command. With Common SPI Command, ESP32 can also provide
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* a way to use same Common SPI command groups on different
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* Flash chips.
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* 5. This functions are not protected by packeting, Please use the
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*************************************************************
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*/
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#define PERIPHS_SPI_FLASH_CMD SPI_MEM_CMD_REG(1)
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#define PERIPHS_SPI_FLASH_ADDR SPI_MEM_ADDR_REG(1)
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#define PERIPHS_SPI_FLASH_CTRL SPI_MEM_CTRL_REG(1)
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#define PERIPHS_SPI_FLASH_CTRL1 SPI_MEM_CTRL1_REG(1)
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#define PERIPHS_SPI_FLASH_STATUS SPI_MEM_RD_STATUS_REG(1)
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#define PERIPHS_SPI_FLASH_USRREG SPI_MEM_USER_REG(1)
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#define PERIPHS_SPI_FLASH_USRREG1 SPI_MEM_USER1_REG(1)
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#define PERIPHS_SPI_FLASH_USRREG2 SPI_MEM_USER2_REG(1)
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#define PERIPHS_SPI_FLASH_C0 SPI_MEM_W0_REG(1)
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#define PERIPHS_SPI_FLASH_C1 SPI_MEM_W1_REG(1)
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#define PERIPHS_SPI_FLASH_C2 SPI_MEM_W2_REG(1)
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#define PERIPHS_SPI_FLASH_C3 SPI_MEM_W3_REG(1)
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#define PERIPHS_SPI_FLASH_C4 SPI_MEM_W4_REG(1)
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#define PERIPHS_SPI_FLASH_C5 SPI_MEM_W5_REG(1)
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#define PERIPHS_SPI_FLASH_C6 SPI_MEM_W6_REG(1)
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#define PERIPHS_SPI_FLASH_C7 SPI_MEM_W7_REG(1)
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#define PERIPHS_SPI_FLASH_TX_CRC SPI_MEM_TX_CRC_REG(1)
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#define SPI0_R_QIO_DUMMY_CYCLELEN 5
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#define SPI0_R_QIO_ADDR_BITSLEN 23
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#define SPI0_R_FAST_DUMMY_CYCLELEN 7
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#define SPI0_R_DIO_DUMMY_CYCLELEN 3
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#define SPI0_R_FAST_ADDR_BITSLEN 23
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#define SPI0_R_SIO_ADDR_BITSLEN 23
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#define SPI1_R_QIO_DUMMY_CYCLELEN 5
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#define SPI1_R_QIO_ADDR_BITSLEN 23
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#define SPI1_R_FAST_DUMMY_CYCLELEN 7
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#define SPI1_R_DIO_DUMMY_CYCLELEN 3
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#define SPI1_R_DIO_ADDR_BITSLEN 23
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#define SPI1_R_FAST_ADDR_BITSLEN 23
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#define SPI1_R_SIO_ADDR_BITSLEN 23
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#define ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN 23
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#define ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN SPI_MEM_WRSR_2B
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//SPI address register
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#define ESP_ROM_SPIFLASH_BYTES_LEN 24
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#define ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM 32
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#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM 16
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#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS 0xf
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//SPI status register
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#define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0
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#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1
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#define ESP_ROM_SPIFLASH_BP0 BIT2
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#define ESP_ROM_SPIFLASH_BP1 BIT3
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#define ESP_ROM_SPIFLASH_BP2 BIT4
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#define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2)
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#define ESP_ROM_SPIFLASH_QE BIT9
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#define FLASH_ID_GD25LQ32C 0xC86016
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/**
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* @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed.
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* Please do not call this function in SDK.
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*
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* @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write).
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*
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* @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M.
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*
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* @return None
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*/
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void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv);
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/**
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* @brief Select SPI Flash to QIO mode when WP pad is read from Flash.
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* Please do not call this function in SDK.
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*
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* @param uint8_t wp_gpio_num: WP gpio number.
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*
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* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
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* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
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*
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* @return None
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*/
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void esp_rom_spiflash_select_qiomode(uint8_t wp_gpio_num, uint32_t ishspi);
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/**
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* @brief Set SPI Flash pad drivers.
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* Please do not call this function in SDK.
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*
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* @param uint8_t wp_gpio_num: WP gpio number.
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*
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* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
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* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
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*
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* @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid
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* drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp.
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* Values usually read from falsh by rom code, function usually callde by rom code.
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* if value with bit(3) set, the value is valid, bit[2:0] is the real value.
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*
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* @return None
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*/
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void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs);
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/**
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* @brief Select SPI Flash function for pads.
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* Please do not call this function in SDK.
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*
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* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
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* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
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*
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* @return None
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*/
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void esp_rom_spiflash_select_padsfunc(uint32_t ishspi);
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/**
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* @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD.
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* Please do not call this function in SDK.
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*
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* @param esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command.
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*
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* @return uint16_t 0 : do not send command any more.
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* 1 : go to the next command.
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* n > 1 : skip (n - 1) commands.
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*/
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uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd);
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#ifdef __cplusplus
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}
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#endif
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