mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
874a720286
update all struct headers to be more "standardized":
- bit fields are properly wrapped with struct
- bitwidth sum should be 32 within same struct, so that it's correctly padded with reserved bits
- bit field should be uint32_t
- typedef volatile struct xxx{} yyy;: xxx must exists. refer: https://github.com/espressif/esp-idf/pull/3199
added helper macros to force peripheral registers being accessed in 32 bitwidth
added a check script into ci
185 lines
11 KiB
C
185 lines
11 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_PCNT_STRUCT_H_
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#define _SOC_PCNT_STRUCT_H_
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef volatile struct pcnt_dev_s {
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struct {
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union {
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struct {
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uint32_t filter_thres: 10; /*This register is used to filter pulse whose width is smaller than this value for unit0.*/
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uint32_t filter_en: 1; /*This is the enable bit for filtering input signals for unit0.*/
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uint32_t thr_zero_en: 1; /*This is the enable bit for comparing unit0's count with 0 value.*/
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uint32_t thr_h_lim_en: 1; /*This is the enable bit for comparing unit0's count with thr_h_lim value.*/
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uint32_t thr_l_lim_en: 1; /*This is the enable bit for comparing unit0's count with thr_l_lim value.*/
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uint32_t thr_thres0_en: 1; /*This is the enable bit for comparing unit0's count with thres0 value.*/
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uint32_t thr_thres1_en: 1; /*This is the enable bit for comparing unit0's count with thres1 value .*/
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uint32_t ch0_neg_mode: 2; /*This register is used to control the mode of channel0's input neg-edge signal for unit0. 2'd1：increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/
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uint32_t ch0_pos_mode: 2; /*This register is used to control the mode of channel0's input pos-edge signal for unit0. 2'd1：increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/
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uint32_t ch0_hctrl_mode: 2; /*This register is used to control the mode of channel0's high control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/
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uint32_t ch0_lctrl_mode: 2; /*This register is used to control the mode of channel0's low control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/
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uint32_t ch1_neg_mode: 2; /*This register is used to control the mode of channel1's input neg-edge signal for unit0. 2'd1：increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/
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uint32_t ch1_pos_mode: 2; /*This register is used to control the mode of channel1's input pos-edge signal for unit0. 2'd1：increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/
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uint32_t ch1_hctrl_mode: 2; /*This register is used to control the mode of channel1's high control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/
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uint32_t ch1_lctrl_mode: 2; /*This register is used to control the mode of channel1's low control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/
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};
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uint32_t val;
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} conf0;
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union {
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struct {
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uint32_t cnt_thres0:16; /*This register is used to configure thres0 value for unit0.*/
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uint32_t cnt_thres1:16; /*This register is used to configure thres1 value for unit0.*/
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};
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uint32_t val;
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} conf1;
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union {
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struct {
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uint32_t cnt_h_lim:16; /*This register is used to configure thr_h_lim value for unit0.*/
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uint32_t cnt_l_lim:16; /*This register is used to configure thr_l_lim value for unit0.*/
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};
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uint32_t val;
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} conf2;
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} conf_unit[8];
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union {
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struct {
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uint32_t cnt_val : 16; /*This register stores the current pulse count value for unit0.*/
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uint32_t reserved16: 16;
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};
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uint32_t val;
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} cnt_unit[8];
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union {
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struct {
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uint32_t cnt_thr_event_u0: 1; /*This is the interrupt raw bit for channel0 event.*/
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uint32_t cnt_thr_event_u1: 1; /*This is the interrupt raw bit for channel1 event.*/
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uint32_t cnt_thr_event_u2: 1; /*This is the interrupt raw bit for channel2 event.*/
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uint32_t cnt_thr_event_u3: 1; /*This is the interrupt raw bit for channel3 event.*/
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uint32_t cnt_thr_event_u4: 1; /*This is the interrupt raw bit for channel4 event.*/
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uint32_t cnt_thr_event_u5: 1; /*This is the interrupt raw bit for channel5 event.*/
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uint32_t cnt_thr_event_u6: 1; /*This is the interrupt raw bit for channel6 event.*/
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uint32_t cnt_thr_event_u7: 1; /*This is the interrupt raw bit for channel7 event.*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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} int_raw;
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union {
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struct {
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uint32_t cnt_thr_event_u0: 1; /*This is the interrupt status bit for channel0 event.*/
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uint32_t cnt_thr_event_u1: 1; /*This is the interrupt status bit for channel1 event.*/
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uint32_t cnt_thr_event_u2: 1; /*This is the interrupt status bit for channel2 event.*/
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uint32_t cnt_thr_event_u3: 1; /*This is the interrupt status bit for channel3 event.*/
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uint32_t cnt_thr_event_u4: 1; /*This is the interrupt status bit for channel4 event.*/
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uint32_t cnt_thr_event_u5: 1; /*This is the interrupt status bit for channel5 event.*/
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uint32_t cnt_thr_event_u6: 1; /*This is the interrupt status bit for channel6 event.*/
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uint32_t cnt_thr_event_u7: 1; /*This is the interrupt status bit for channel7 event.*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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} int_st;
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union {
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struct {
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uint32_t cnt_thr_event_u0: 1; /*This is the interrupt enable bit for channel0 event.*/
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uint32_t cnt_thr_event_u1: 1; /*This is the interrupt enable bit for channel1 event.*/
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uint32_t cnt_thr_event_u2: 1; /*This is the interrupt enable bit for channel2 event.*/
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uint32_t cnt_thr_event_u3: 1; /*This is the interrupt enable bit for channel3 event.*/
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uint32_t cnt_thr_event_u4: 1; /*This is the interrupt enable bit for channel4 event.*/
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uint32_t cnt_thr_event_u5: 1; /*This is the interrupt enable bit for channel5 event.*/
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uint32_t cnt_thr_event_u6: 1; /*This is the interrupt enable bit for channel6 event.*/
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uint32_t cnt_thr_event_u7: 1; /*This is the interrupt enable bit for channel7 event.*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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} int_ena;
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union {
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struct {
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uint32_t cnt_thr_event_u0: 1; /*Set this bit to clear channel0 event interrupt.*/
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uint32_t cnt_thr_event_u1: 1; /*Set this bit to clear channel1 event interrupt.*/
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uint32_t cnt_thr_event_u2: 1; /*Set this bit to clear channel2 event interrupt.*/
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uint32_t cnt_thr_event_u3: 1; /*Set this bit to clear channel3 event interrupt.*/
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uint32_t cnt_thr_event_u4: 1; /*Set this bit to clear channel4 event interrupt.*/
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uint32_t cnt_thr_event_u5: 1; /*Set this bit to clear channel5 event interrupt.*/
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uint32_t cnt_thr_event_u6: 1; /*Set this bit to clear channel6 event interrupt.*/
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uint32_t cnt_thr_event_u7: 1; /*Set this bit to clear channel7 event interrupt.*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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} int_clr;
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union {
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struct {
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uint32_t cnt_mode:2; /*0: positive value to zero; 1: negative value to zero; 2: counter value negative ; 3: counter value positive*/
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uint32_t thres1_lat:1; /* counter value equals to thresh1*/
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uint32_t thres0_lat:1; /* counter value equals to thresh0*/
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uint32_t l_lim_lat:1; /* counter value reaches h_lim*/
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uint32_t h_lim_lat:1; /* counter value reaches l_lim*/
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uint32_t zero_lat:1; /* counter value equals zero*/
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uint32_t reserved7:25;
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};
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uint32_t val;
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} status_unit[8];
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union {
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struct {
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uint32_t cnt_rst_u0: 1; /*Set this bit to clear unit0's counter.*/
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uint32_t cnt_pause_u0: 1; /*Set this bit to pause unit0's counter.*/
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uint32_t cnt_rst_u1: 1; /*Set this bit to clear unit1's counter.*/
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uint32_t cnt_pause_u1: 1; /*Set this bit to pause unit1's counter.*/
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uint32_t cnt_rst_u2: 1; /*Set this bit to clear unit2's counter.*/
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uint32_t cnt_pause_u2: 1; /*Set this bit to pause unit2's counter.*/
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uint32_t cnt_rst_u3: 1; /*Set this bit to clear unit3's counter.*/
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uint32_t cnt_pause_u3: 1; /*Set this bit to pause unit3's counter.*/
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uint32_t cnt_rst_u4: 1; /*Set this bit to clear unit4's counter.*/
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uint32_t cnt_pause_u4: 1; /*Set this bit to pause unit4's counter.*/
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uint32_t cnt_rst_u5: 1; /*Set this bit to clear unit5's counter.*/
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uint32_t cnt_pause_u5: 1; /*Set this bit to pause unit5's counter.*/
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uint32_t cnt_rst_u6: 1; /*Set this bit to clear unit6's counter.*/
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uint32_t cnt_pause_u6: 1; /*Set this bit to pause unit6's counter.*/
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uint32_t cnt_rst_u7: 1; /*Set this bit to clear unit7's counter.*/
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uint32_t cnt_pause_u7: 1; /*Set this bit to pause unit7's counter.*/
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uint32_t clk_en: 1;
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uint32_t reserved17: 15;
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};
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uint32_t val;
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} ctrl;
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uint32_t reserved_b4;
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uint32_t reserved_b8;
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uint32_t reserved_bc;
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uint32_t reserved_c0;
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uint32_t reserved_c4;
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uint32_t reserved_c8;
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uint32_t reserved_cc;
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uint32_t reserved_d0;
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uint32_t reserved_d4;
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uint32_t reserved_d8;
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uint32_t reserved_dc;
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uint32_t reserved_e0;
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uint32_t reserved_e4;
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uint32_t reserved_e8;
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uint32_t reserved_ec;
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uint32_t reserved_f0;
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uint32_t reserved_f4;
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uint32_t reserved_f8;
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uint32_t date; /**/
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} pcnt_dev_t;
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extern pcnt_dev_t PCNT;
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#ifdef __cplusplus
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}
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#endif
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#endif /* _SOC_PCNT_STRUCT_H_ */
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