mirror of
https://github.com/espressif/esp-idf.git
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333553caf2
fix(hal/include): fix header violations in hal component fix(hal/include): Move type definitions from `xx_hal.h` to `xx_types.h` fix(hal/include): Move type definitions from `xx_hal.h` to `xx_types.h` fix(hal/include): Add comment for a far away `#endif` fix(hal/include): change scope for cpp guard ci: Remove components/hal/ comment from public headers check exceptions Add missing include macro sdkconfig.h for header files Add missing include macro stdbool.h for header files Add missing include macro stdint.h for header files Add missing capability guard macro for header files Add missing cpp guard macro for header files Remove some useless include macros Add some missing `inline` attribute for functions defined in header files Remove components/hal/ from public headers check exceptions fix(hal/include): fix invalid licenses fix(hal/include): fix invalid licenses fix(hal/include): add missing soc_caps.h fix(hal): include soc_caps.h before cap macro is used fix(hal): Remove unnecessary target check fix(hal): fix header and macro problems Add missing include macro Remove loop dependency in hal Add comment for far-away endif fix(hal): Add missing soc_caps.h ci: update check_copyright_ignore.txt Change the sequence of `#include` macro, cpp guard macro Change the wrap scope of capacity macro fix(hal): Change position of C++ guard to pass test
390 lines
17 KiB
C
390 lines
17 KiB
C
/*
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* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include <stdbool.h>
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#include "esp_assert.h"
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#include "esp_err.h"
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#include "hal/eth_types.h"
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#include "soc/soc_caps.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if SOC_EMAC_SUPPORTED
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#include "hal/emac_ll.h"
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/**
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* @brief Indicate to ::emac_hal_receive_frame that receive frame buffer was allocated by ::emac_hal_alloc_recv_buf
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*
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*/
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#define EMAC_HAL_BUF_SIZE_AUTO 0
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/**
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* @brief Ethernet DMA TX Descriptor
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*
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*/
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typedef struct {
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volatile union {
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struct {
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uint32_t Deferred : 1; /*!< MAC defers before transmission */
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uint32_t UnderflowErr : 1; /*!< DMA encountered an empty transmit buffer */
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uint32_t ExcessiveDeferral : 1; /*!< Excessive deferral of over 24,288 bit times */
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uint32_t CollisionCount : 4; /*!< Number of collisions occurred before transmitted */
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uint32_t VLanFrame : 1; /*!< Transmitted frame is a VLAN-type frame */
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uint32_t ExcessiveCollision : 1; /*!< Transmission aborted after 16 successive collisions */
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uint32_t LateCollision : 1; /*!< Collision occurred after the collision window */
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uint32_t NoCarrier : 1; /*!< Carrier Sense signal from the PHY was not asserted */
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uint32_t LossCarrier : 1; /*!< Loss of carrier occurred during transmission */
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uint32_t PayloadChecksumErr : 1; /*!< Checksum error in TCP/UDP/ICMP datagram payload */
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uint32_t FrameFlushed : 1; /*!< DMA or MTL flushed the frame */
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uint32_t JabberTimeout : 1; /*!< MAC transmitter has experienced a jabber timeout */
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uint32_t ErrSummary : 1; /*!< Error Summary */
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uint32_t IPHeadErr : 1; /*!< IP Header Error */
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uint32_t TxTimestampStatus : 1; /*!< Timestamp captured for the transmit frame */
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uint32_t VLANInsertControl : 2; /*!< VLAN tagging or untagging before transmitting */
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uint32_t SecondAddressChained : 1; /*!< Second address in the descriptor is Next Descriptor address */
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uint32_t TransmitEndRing : 1; /*!< Descriptor list reached its final descriptor */
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uint32_t ChecksumInsertControl : 2; /*!< Control checksum calculation and insertion */
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uint32_t CRCReplacementControl : 1; /*!< Control CRC replace */
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uint32_t TransmitTimestampEnable : 1; /*!< Enable IEEE1588 harware timestamping */
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uint32_t DisablePad : 1; /*!< Control add padding when frame short than 64 bytes */
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uint32_t DisableCRC : 1; /*!< Control append CRC to the end of frame */
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uint32_t FirstSegment : 1; /*!< Buffer contains the first segment of a frame */
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uint32_t LastSegment : 1; /*!< Buffer contains the last segment of a frame */
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uint32_t InterruptOnComplete : 1; /*!< Interrupt after frame transmitted */
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uint32_t Own : 1; /*!< Owner of this descriptor: DMA controller or host */
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};
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uint32_t Value;
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} TDES0;
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union {
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struct {
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uint32_t TransmitBuffer1Size : 13; /*!< First data buffer byte size */
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uint32_t Reserved : 3; /*!< Reserved */
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uint32_t TransmitBuffer2Size : 13; /*!< Second data buffer byte size */
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uint32_t SAInsertControl : 3; /*!< Control MAC add or replace Source Address field */
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};
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uint32_t Value;
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} TDES1;
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uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
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uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
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uint32_t Reserved1; /*!< Reserved */
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uint32_t Reserved2; /*!< Reserved */
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uint32_t TimeStampLow; /*!< Transmit Frame Timestamp Low */
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uint32_t TimeStampHigh; /*!< Transmit Frame Timestamp High */
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} eth_dma_tx_descriptor_t;
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#define EMAC_DMATXDESC_CHECKSUM_BYPASS 0 /*!< Checksum engine bypass */
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#define EMAC_DMATXDESC_CHECKSUM_IPV4HEADER 1 /*!< IPv4 header checksum insertion */
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#define EMAC_DMATXDESC_CHECKSUM_TCPUDPICMPSEGMENT 2 /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
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#define EMAC_DMATXDESC_CHECKSUM_TCPUDPICMPFULL 3 /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
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ESP_STATIC_ASSERT(sizeof(eth_dma_tx_descriptor_t) == 32, "eth_dma_tx_descriptor_t should occupy 32 bytes in memory");
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/**
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* @brief Ethernet DMA RX Descriptor
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*
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*/
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typedef struct {
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volatile union {
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struct {
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uint32_t ExtendStatusAvailable : 1; /*!< Extended statsu is available in RDES4 */
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uint32_t CRCErr : 1; /*!< CRC error occurred on frame */
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uint32_t DribbleBitErr : 1; /*!< frame contains non int multiple of 8 bits */
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uint32_t ReceiveErr : 1; /*!< Receive error */
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uint32_t ReceiveWatchdogTimeout : 1; /*!< Receive Watchdog timeout */
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uint32_t FrameType : 1; /*!< Ethernet type or IEEE802.3 */
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uint32_t LateCollision : 1; /*!< Late collision occurred during reception */
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uint32_t TSAvailIPChecksumErrGiantFrame : 1; /*!< Timestamp available or IP Checksum error or Giant frame */
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uint32_t LastDescriptor : 1; /*!< Last buffer of the frame */
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uint32_t FirstDescriptor : 1; /*!< First buffer of the frame */
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uint32_t VLANTag : 1; /*!< VLAN Tag: received frame is a VLAN frame */
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uint32_t OverflowErr : 1; /*!< Frame was damaged due to buffer overflow */
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uint32_t LengthErr : 1; /*!< Frame size not matching with length field */
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uint32_t SourceAddrFilterFail : 1; /*!< SA field of frame failed the SA filter */
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uint32_t DescriptorErr : 1; /*!< Frame truncated and DMA doesn't own next descriptor */
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uint32_t ErrSummary : 1; /*!< Error Summary, OR of all errors in RDES */
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uint32_t FrameLength : 14; /*!< Byte length of received frame */
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uint32_t DestinationAddrFilterFail : 1; /*!< Frame failed in the DA Filter in the MAC */
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uint32_t Own : 1; /*!< Owner of this descriptor: DMA controller or host */
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};
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uint32_t Value;
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} RDES0;
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union {
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struct {
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uint32_t ReceiveBuffer1Size : 13; /*!< First data buffer size in bytes */
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uint32_t Reserved1 : 1; /*!< Reserved */
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uint32_t SecondAddressChained : 1; /*!< Seconde address is the Next Descriptor address */
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uint32_t ReceiveEndOfRing : 1; /*!< Descriptor reached its final descriptor */
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uint32_t ReceiveBuffer2Size : 13; /*!< Second data buffer size in bytes */
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uint32_t Reserved : 2; /*!< Reserved */
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uint32_t DisableInterruptOnComplete : 1; /*!< Disable the assertion of interrupt to host */
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};
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uint32_t Value;
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} RDES1;
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uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
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uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
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volatile union {
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struct {
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uint32_t IPPayloadType : 3; /*!< Type of payload in the IP datagram */
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uint32_t IPHeadErr : 1; /*!< IP header error */
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uint32_t IPPayloadErr : 1; /*!< IP payload error */
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uint32_t IPChecksumBypass : 1; /*!< Checksum offload engine is bypassed */
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uint32_t IPv4PacketReceived : 1; /*!< Received packet is an IPv4 packet */
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uint32_t IPv6PacketReceived : 1; /*!< Received packet is an IPv6 packet */
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uint32_t MessageType : 4; /*!< PTP Message Type */
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uint32_t PTPFrameType : 1; /*!< PTP message is over Ethernet or IPv4/IPv6 */
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uint32_t PTPVersion : 1; /*!< Version of PTP protocol */
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uint32_t TimestampDropped : 1; /*!< Timestamp dropped because of overflow */
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uint32_t Reserved1 : 1; /*!< Reserved */
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uint32_t AVPacketReceived : 1; /*!< AV packet is received */
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uint32_t AVTaggedPacketReceived : 1; /*!< AV tagged packet is received */
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uint32_t VLANTagPrioVal : 3; /*!< VLAN tag's user value in the received packekt */
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uint32_t Reserved2 : 3; /*!< Reserved */
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uint32_t Layer3FilterMatch : 1; /*!< Received frame matches one of the enabled Layer3 IP */
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uint32_t Layer4FilterMatch : 1; /*!< Received frame matches one of the enabled Layer4 IP */
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uint32_t Layer3Layer4FilterNumberMatch : 2; /*!< Number of Layer3 and Layer4 Filter that matches the received frame */
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uint32_t Reserved3 : 4; /*!< Reserved */
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};
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uint32_t Value;
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} ExtendedStatus;
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uint32_t Reserved; /*!< Reserved */
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uint32_t TimeStampLow; /*!< Receive frame timestamp low */
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uint32_t TimeStampHigh; /*!< Receive frame timestamp high */
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} eth_dma_rx_descriptor_t;
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ESP_STATIC_ASSERT(sizeof(eth_dma_rx_descriptor_t) == 32, "eth_dma_rx_descriptor_t should occupy 32 bytes in memory");
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typedef struct emac_mac_dev_s *emac_mac_soc_regs_t;
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typedef struct emac_dma_dev_s *emac_dma_soc_regs_t;
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typedef struct emac_ext_dev_s *emac_ext_soc_regs_t;
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typedef struct {
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emac_mac_soc_regs_t mac_regs;
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emac_dma_soc_regs_t dma_regs;
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emac_ext_soc_regs_t ext_regs;
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uint8_t **rx_buf;
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uint8_t **tx_buf;
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void *descriptors;
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eth_dma_rx_descriptor_t *rx_desc;
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eth_dma_tx_descriptor_t *tx_desc;
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} emac_hal_context_t;
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/**
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* @brief EMAC related configuration
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*/
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typedef struct {
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eth_mac_dma_burst_len_t dma_burst_len; /*!< eth-type enum of chosen dma burst-len */
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} emac_hal_dma_config_t;
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void emac_hal_init(emac_hal_context_t *hal, void *descriptors,
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uint8_t **rx_buf, uint8_t **tx_buf);
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void emac_hal_iomux_init_mii(void);
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void emac_hal_iomux_init_rmii(void);
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void emac_hal_iomux_rmii_clk_input(void);
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void emac_hal_iomux_rmii_clk_ouput(int num);
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void emac_hal_iomux_init_tx_er(void);
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void emac_hal_iomux_init_rx_er(void);
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static inline void emac_hal_clock_enable_mii(emac_hal_context_t *hal)
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{
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emac_ll_clock_enable_mii(hal->ext_regs);
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}
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static inline void emac_hal_clock_enable_rmii_input(emac_hal_context_t *hal)
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{
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emac_ll_clock_enable_rmii_input(hal->ext_regs);
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}
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static inline void emac_hal_clock_enable_rmii_output(emac_hal_context_t *hal)
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{
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emac_ll_clock_enable_rmii_output(hal->ext_regs);
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}
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void emac_hal_reset_desc_chain(emac_hal_context_t *hal);
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static inline void *emac_hal_get_desc_chain(emac_hal_context_t *hal)
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{
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return hal->descriptors;
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}
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static inline void emac_hal_reset(emac_hal_context_t *hal)
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{
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emac_ll_reset(hal->dma_regs);
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}
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static inline bool emac_hal_is_reset_done(emac_hal_context_t *hal)
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{
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return emac_ll_is_reset_done(hal->dma_regs);
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}
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void emac_hal_set_csr_clock_range(emac_hal_context_t *hal, int freq);
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void emac_hal_init_mac_default(emac_hal_context_t *hal);
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void emac_hal_init_dma_default(emac_hal_context_t *hal, emac_hal_dma_config_t *hal_config);
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static inline void emac_hal_set_speed(emac_hal_context_t *hal, eth_speed_t speed)
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{
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emac_ll_set_port_speed(hal->mac_regs, speed);
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}
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static inline void emac_hal_set_duplex(emac_hal_context_t *hal, eth_duplex_t duplex)
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{
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emac_ll_set_duplex(hal->mac_regs, duplex);
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}
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static inline void emac_hal_set_promiscuous(emac_hal_context_t *hal, bool enable)
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{
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emac_ll_promiscuous_mode_enable(hal->mac_regs, enable);
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}
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/**
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* @brief Send MAC-CTRL frames to peer (EtherType=0x8808, opcode=0x0001, dest_addr=MAC-specific-ctrl-proto-01 (01:80:c2:00:00:01))
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*/
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static inline void emac_hal_send_pause_frame(emac_hal_context_t *hal, bool enable)
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{
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emac_ll_pause_frame_enable(hal->ext_regs, enable);
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}
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static inline bool emac_hal_is_mii_busy(emac_hal_context_t *hal)
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{
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return emac_ll_is_mii_busy(hal->mac_regs);
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}
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void emac_hal_set_phy_cmd(emac_hal_context_t *hal, uint32_t phy_addr, uint32_t phy_reg, bool write);
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static inline void emac_hal_set_phy_data(emac_hal_context_t *hal, uint32_t reg_value)
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{
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emac_ll_set_phy_data(hal->mac_regs, reg_value);
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}
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static inline uint32_t emac_hal_get_phy_data(emac_hal_context_t *hal)
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{
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return emac_ll_get_phy_data(hal->mac_regs);
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}
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void emac_hal_set_address(emac_hal_context_t *hal, uint8_t *mac_addr);
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/**
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* @brief Starts EMAC Transmission & Reception
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*
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* @param hal EMAC HAL context infostructure
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*/
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void emac_hal_start(emac_hal_context_t *hal);
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/**
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* @brief Stops EMAC Transmission & Reception
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*
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* @param hal EMAC HAL context infostructure
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* @return
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* - ESP_OK: succeed
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* - ESP_ERR_INVALID_STATE: previous frame transmission/reception is not completed. When this error occurs,
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* wait and reapeat the EMAC stop again.
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*/
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esp_err_t emac_hal_stop(emac_hal_context_t *hal);
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/**
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* @brief Transmit data from buffer over EMAC
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*
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* @param[in] hal EMAC HAL context infostructure
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* @param[in] buf buffer to be transmitted
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* @param[in] length length of the buffer
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* @return number of transmitted bytes when success
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*/
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uint32_t emac_hal_transmit_frame(emac_hal_context_t *hal, uint8_t *buf, uint32_t length);
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/**
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* @brief Transmit data from multiple buffers over EMAC in single Ethernet frame. Data will be joint into
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* single frame in order in which the buffers are stored in input array.
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*
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* @param[in] hal EMAC HAL context infostructure
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* @param[in] buffs array of pointers to buffers to be transmitted
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* @param[in] lengths array of lengths of the buffers
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* @param[in] inbuffs_cnt number of buffers (i.e. input arrays size)
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* @return number of transmitted bytes when success
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*
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* @pre @p lengths array must have the same size as @p buffs array and their elements need to be stored in the same
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* order, i.e. lengths[1] is a length assocaited with data buffer referenced at buffs[1] position.
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*/
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uint32_t emac_hal_transmit_multiple_buf_frame(emac_hal_context_t *hal, uint8_t **buffs, uint32_t *lengths, uint32_t inbuffs_cnt);
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/**
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* @brief Allocate buffer with size equal to actually received Ethernet frame size.
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*
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* @param[in] hal EMAC HAL context infostructure
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* @param[in, out] size as an input defines maximum size of buffer to be allocated. As an output, indicates actual size of received
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* Ethernet frame which is waiting to be processed. Returned size may be 0 when there is no waiting frame.
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*
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* @note If maximum allowed size of buffer to be allocated is less than actual size of received Ethernet frame, the buffer
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* is allocated with that limit and the frame will be truncated by emac_hal_receive_frame.
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*
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* @return Pointer to allocated buffer
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* NULL when allocation fails or when there is no waiting Ethernet frame
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*/
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uint8_t *emac_hal_alloc_recv_buf(emac_hal_context_t *hal, uint32_t *size);
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/**
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* @brief Copy received Ethernet frame from EMAC DMA memory space to application.
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*
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* @param[in] hal EMAC HAL context infostructure
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* @param[in] buf buffer into which the Ethernet frame is to be copied
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* @param[in] size buffer size. When buffer was allocated by ::emac_hal_alloc_recv_buf, this parameter needs to be set
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* to EMAC_HAL_BUF_SIZE_AUTO
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* @param[out] frames_remain number of frames remaining to be processed
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* @param[out] free_desc muber of free DMA Rx descriptors
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*
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* @return number of copied bytes when success
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* 0 when there is no waiting Ethernet frame or on error
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*
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* @note FCS field is never copied
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* @note If buffer size is less than actual size of received Ethernet frame, the frame will be truncated.
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* @note When this function is called with EMAC_HAL_BUF_SIZE_AUTO size parameter, buffer needs to be allocated by
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* ::emac_hal_alloc_recv_buf function at first.
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*/
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uint32_t emac_hal_receive_frame(emac_hal_context_t *hal, uint8_t *buf, uint32_t size, uint32_t *frames_remain, uint32_t *free_desc);
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uint32_t emac_hal_flush_recv_frame(emac_hal_context_t *hal, uint32_t *frames_remain, uint32_t *free_desc);
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void emac_hal_enable_flow_ctrl(emac_hal_context_t *hal, bool enable);
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static inline uint32_t emac_hal_get_intr_enable_status(emac_hal_context_t *hal)
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{
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return emac_ll_get_intr_enable_status(hal->dma_regs);
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}
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static inline uint32_t emac_hal_get_intr_status(emac_hal_context_t *hal)
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{
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return emac_ll_get_intr_status(hal->dma_regs);
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}
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static inline void emac_hal_clear_corresponding_intr(emac_hal_context_t *hal, uint32_t bits)
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{
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emac_ll_clear_corresponding_intr(hal->dma_regs, bits);
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}
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static inline void emac_hal_clear_all_intr(emac_hal_context_t *hal)
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{
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emac_ll_clear_all_pending_intr(hal->dma_regs);
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}
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#endif // SOC_EMAC_SUPPORTED
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#ifdef __cplusplus
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}
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#endif
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