gaoxu afe3bfe19f SPI:fix spi slave example sender ccount issue
On riscv core, core cycle counter counts the clock cycles only when core is active (not sleeping).
In spi_slave/sender example, it uses ccount (core cycle counter) to do a simple debounce.
Therefore, when using spi_slave/sender and spi_slave/receiver, program will be stuck.
This commit fix this issue by using esp_timer
2022-06-22 15:06:29 +08:00
..
2021-10-09 13:58:24 +08:00
2021-10-09 13:58:24 +08:00
2021-10-02 14:23:31 +08:00
2021-06-21 14:02:14 +08:00

Peripherals Examples

This section provides examples how to configure and use ESP32s internal peripherals like GPIO, UART, I2C, SPI, timers, counters, ADC / DAC, PWM, etc.

See the README.md file in the upper level examples directory for more information about examples.