mirror of
https://github.com/espressif/esp-idf.git
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450 lines
16 KiB
C
450 lines
16 KiB
C
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include <stdbool.h>
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#include "soc/memprot_defs.h"
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#include "hal/memprot_types.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* ========================================================================================
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* === PeriBus1 common
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* ========================================================================================
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*/
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static inline void memprot_ll_peri1_clear_intr(void)
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{
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DPORT_SET_PERI_REG_MASK(DPORT_PMS_PRO_DPORT_6_REG, DPORT_PMS_PRO_DPORT_ILG_CLR);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PMS_PRO_DPORT_6_REG, DPORT_PMS_PRO_DPORT_ILG_CLR);
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}
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static inline uint32_t memprot_ll_peri1_get_intr_source_num(void)
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{
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return ETS_PMS_PRO_DPORT_ILG_INTR_SOURCE;
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}
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static inline void memprot_ll_peri1_intr_ena(bool enable)
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{
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if (enable) {
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DPORT_SET_PERI_REG_MASK(DPORT_PMS_PRO_DPORT_6_REG, DPORT_PMS_PRO_DPORT_ILG_EN);
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} else {
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PMS_PRO_DPORT_6_REG, DPORT_PMS_PRO_DPORT_ILG_EN);
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}
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}
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static inline uint32_t memprot_ll_peri1_get_ctrl_reg(void)
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{
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return DPORT_READ_PERI_REG(DPORT_PMS_PRO_DPORT_6_REG);
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}
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static inline uint32_t memprot_ll_peri1_get_fault_reg(void)
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{
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return DPORT_READ_PERI_REG(DPORT_PMS_PRO_DPORT_7_REG);
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}
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static inline void memprot_ll_peri1_get_fault_op_type(uint32_t *op_type, uint32_t *op_subtype)
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{
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uint32_t status_bits = memprot_ll_peri1_get_fault_reg();
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//*op_type = (uint32_t)status_bits & PERI1_INTR_ST_OP_RW_BIT;
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*op_type = 0;
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//! DPORT_PMS_PRO_DPORT_7_REG is missing op_type bit
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*op_subtype = (uint32_t)status_bits & PERI1_INTR_ST_OP_TYPE_BIT;
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}
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static inline bool memprot_ll_peri1_is_assoc_intr(void)
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{
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return DPORT_GET_PERI_REG_MASK(DPORT_PMS_PRO_DPORT_7_REG, DPORT_PMS_PRO_DPORT_ILG_INTR) > 0;
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}
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static inline uint32_t memprot_ll_peri1_get_intr_ena_bit(void)
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{
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return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DPORT_6_REG, DPORT_PMS_PRO_DPORT_ILG_EN);
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}
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static inline uint32_t memprot_ll_peri1_get_intr_on_bit(void)
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{
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return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DPORT_6_REG, DPORT_PMS_PRO_DPORT_ILG_INTR);
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}
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static inline uint32_t memprot_ll_peri1_get_intr_clr_bit(void)
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{
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return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DPORT_6_REG, DPORT_PMS_PRO_DPORT_ILG_CLR);
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}
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static inline uint32_t memprot_ll_peri1_get_lock_reg(void)
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{
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return DPORT_READ_PERI_REG(DPORT_PMS_PRO_DPORT_0_REG);
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}
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//resets automatically on CPU restart
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static inline void memprot_ll_peri1_set_lock(void)
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{
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DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_DPORT_0_REG, DPORT_PMS_PRO_DPORT_LOCK);
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}
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static inline uint32_t memprot_ll_peri1_get_lock_bit(void)
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{
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return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DPORT_0_REG, DPORT_PMS_PRO_DPORT_LOCK);
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}
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/**
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* ========================================================================================
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* === PeriBus1 RTC SLOW
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* ========================================================================================
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*/
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static inline intptr_t memprot_ll_peri1_rtcslow_get_fault_address(void)
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{
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uint32_t status_bits = memprot_ll_peri1_get_fault_reg();
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uint32_t fault_address = (status_bits & PERI1_INTR_ST_FAULTADDR_M) >> PERI1_INTR_ST_FAULTADDR_S;
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uint32_t high_bits = (status_bits & PERI1_INTR_ST_OP_HIGH_BITS) ? PERI1_RTCSLOW_INTR_ST_FAULTADDR_HI_0 : 0;
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return (intptr_t)(fault_address | high_bits);
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}
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static inline bool memprot_ll_peri1_rtcslow_is_intr_mine(void)
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{
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if (memprot_ll_dram0_is_assoc_intr()) {
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uint32_t faulting_address = (uint32_t)memprot_ll_peri1_rtcslow_get_fault_address();
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return faulting_address >= PERI1_RTCSLOW_ADDRESS_LOW && faulting_address <= PERI1_RTCSLOW_ADDRESS_HIGH;
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}
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return false;
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}
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static inline memprot_ll_err_t memprot_ll_peri1_rtcslow_set_prot(uint32_t *split_addr, bool lw, bool lr, bool hw, bool hr)
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{
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uint32_t addr = (uint32_t)split_addr;
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//check corresponding range fit & aligment to 32bit boundaries
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if (addr < PERI1_RTCSLOW_ADDRESS_LOW || addr > PERI1_RTCSLOW_ADDRESS_HIGH) {
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return MEMP_LL_ERR_SPLIT_ADDR_INVALID;
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}
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if (addr % 0x4 != 0) {
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return MEMP_LL_ERR_SPLIT_ADDR_UNALIGNED;
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}
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uint32_t reg_split_addr = PERI1_RTCSLOW_ADDR_TO_CONF_REG(addr);
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//prepare high & low permission mask
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uint32_t permission_mask = 0;
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if (lw) {
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permission_mask |= DPORT_PMS_PRO_DPORT_RTCSLOW_L_W;
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}
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if (lr) {
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permission_mask |= DPORT_PMS_PRO_DPORT_RTCSLOW_L_R;
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}
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if (hw) {
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permission_mask |= DPORT_PMS_PRO_DPORT_RTCSLOW_H_W;
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}
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if (hr) {
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permission_mask |= DPORT_PMS_PRO_DPORT_RTCSLOW_H_R;
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}
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//write PERIBUS1 RTC SLOW cfg register
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DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_DPORT_1_REG, reg_split_addr | permission_mask);
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return MEMP_LL_OK;
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}
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static inline void memprot_ll_peri1_rtcslow_get_split_sgnf_bits(bool *lw, bool *lr, bool *hw, bool *hr)
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{
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*lw = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DPORT_1_REG, DPORT_PMS_PRO_DPORT_RTCSLOW_L_W);
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*lr = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DPORT_1_REG, DPORT_PMS_PRO_DPORT_RTCSLOW_L_R);
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*hw = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DPORT_1_REG, DPORT_PMS_PRO_DPORT_RTCSLOW_H_W);
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*hr = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DPORT_1_REG, DPORT_PMS_PRO_DPORT_RTCSLOW_H_R);
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}
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static inline void memprot_ll_peri1_rtcslow_set_read_perm(bool lr, bool hr)
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{
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DPORT_REG_SET_FIELD(DPORT_PMS_PRO_DPORT_1_REG, DPORT_PMS_PRO_DPORT_RTCSLOW_L_R, lr ? 1 : 0);
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DPORT_REG_SET_FIELD(DPORT_PMS_PRO_DPORT_1_REG, DPORT_PMS_PRO_DPORT_RTCSLOW_H_R, hr ? 1 : 0);
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}
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static inline void memprot_ll_peri1_rtcslow_set_write_perm(bool lw, bool hw)
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{
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DPORT_REG_SET_FIELD(DPORT_PMS_PRO_DPORT_1_REG, DPORT_PMS_PRO_DPORT_RTCSLOW_L_W, lw ? 1 : 0);
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DPORT_REG_SET_FIELD(DPORT_PMS_PRO_DPORT_1_REG, DPORT_PMS_PRO_DPORT_RTCSLOW_H_W, hw ? 1 : 0);
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}
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static inline uint32_t memprot_ll_peri1_rtcslow_get_conf_reg(void)
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{
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return DPORT_READ_PERI_REG(DPORT_PMS_PRO_DPORT_1_REG);
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}
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/**
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* ========================================================================================
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* === PeriBus2 common
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* ========================================================================================
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*/
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static inline void memprot_ll_peri2_clear_intr(void)
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{
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DPORT_SET_PERI_REG_MASK(DPORT_PMS_PRO_AHB_3_REG, DPORT_PMS_PRO_AHB_ILG_CLR);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PMS_PRO_AHB_3_REG, DPORT_PMS_PRO_AHB_ILG_CLR);
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}
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static inline uint32_t memprot_ll_peri2_get_intr_source_num(void)
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{
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return ETS_PMS_PRO_AHB_ILG_INTR_SOURCE;
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}
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static inline void memprot_ll_peri2_intr_ena(bool enable)
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{
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if (enable) {
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DPORT_SET_PERI_REG_MASK(DPORT_PMS_PRO_AHB_3_REG, DPORT_PMS_PRO_AHB_ILG_EN);
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} else {
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PMS_PRO_AHB_3_REG, DPORT_PMS_PRO_AHB_ILG_EN);
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}
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}
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static inline uint32_t memprot_ll_peri2_get_ctrl_reg(void)
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{
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return DPORT_READ_PERI_REG(DPORT_PMS_PRO_AHB_3_REG);
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}
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static inline uint32_t memprot_ll_peri2_get_fault_reg(void)
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{
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return DPORT_READ_PERI_REG(DPORT_PMS_PRO_AHB_4_REG);
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}
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static inline void memprot_ll_peri2_get_fault_op_type(uint32_t *op_type, uint32_t *op_subtype)
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{
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uint32_t status_bits = memprot_ll_peri2_get_fault_reg();
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*op_type = (uint32_t)status_bits & PERI2_INTR_ST_OP_RW_BIT;
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*op_subtype = (uint32_t)status_bits & PERI2_INTR_ST_OP_TYPE_BIT;
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}
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static inline bool memprot_ll_peri2_is_assoc_intr(void)
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{
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return DPORT_GET_PERI_REG_MASK(DPORT_PMS_PRO_AHB_3_REG, DPORT_PMS_PRO_AHB_ILG_INTR) > 0;
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}
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static inline uint32_t memprot_ll_peri2_get_intr_ena_bit(void)
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{
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return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_3_REG, DPORT_PMS_PRO_AHB_ILG_EN);
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}
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static inline uint32_t memprot_ll_peri2_get_intr_on_bit(void)
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{
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return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_3_REG, DPORT_PMS_PRO_AHB_ILG_INTR);
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}
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static inline uint32_t memprot_ll_peri2_get_intr_clr_bit(void)
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{
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return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_3_REG, DPORT_PMS_PRO_AHB_ILG_CLR);
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}
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static inline uint32_t memprot_ll_peri2_get_lock_reg(void)
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{
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return DPORT_READ_PERI_REG(DPORT_PMS_PRO_AHB_0_REG);
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}
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//resets automatically on CPU restart
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static inline void memprot_ll_peri2_set_lock(void)
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{
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DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_AHB_0_REG, DPORT_PMS_PRO_AHB_LOCK);
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}
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static inline uint32_t memprot_ll_peri2_get_lock_bit(void)
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{
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return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_0_REG, DPORT_PMS_PRO_AHB_LOCK);
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}
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static inline intptr_t memprot_ll_peri2_rtcslow_get_fault_address(void)
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{
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uint32_t status_bits = memprot_ll_peri2_get_fault_reg();
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return (intptr_t)(status_bits & PERI2_INTR_ST_FAULTADDR_M);
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}
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/**
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* ========================================================================================
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* === PeriBus2 RTC SLOW 0 (AHB0)
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* ========================================================================================
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*/
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static inline bool memprot_ll_peri2_rtcslow_0_is_intr_mine(void)
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{
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if (memprot_ll_peri2_is_assoc_intr()) {
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uint32_t faulting_address = (uint32_t)memprot_ll_peri2_rtcslow_get_fault_address();
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return faulting_address >= PERI2_RTCSLOW_0_ADDRESS_LOW && faulting_address <= PERI2_RTCSLOW_0_ADDRESS_HIGH;
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}
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return false;
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}
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static inline memprot_ll_err_t memprot_ll_peri2_rtcslow_0_set_prot(uint32_t *split_addr, bool lw, bool lr, bool lx, bool hw, bool hr, bool hx)
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{
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uint32_t addr = (uint32_t)split_addr;
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//check corresponding range fit & aligment to 32bit boundaries
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if (addr < PERI2_RTCSLOW_0_ADDRESS_LOW || addr > PERI2_RTCSLOW_0_ADDRESS_HIGH) {
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return MEMP_LL_ERR_SPLIT_ADDR_INVALID;
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}
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if (addr % 0x4 != 0) {
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return MEMP_LL_ERR_SPLIT_ADDR_UNALIGNED;
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}
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uint32_t reg_split_addr = PERI2_RTCSLOW_0_ADDR_TO_CONF_REG(addr);
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//prepare high & low permission mask
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uint32_t permission_mask = 0;
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if (lw) {
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permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_0_L_W;
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}
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if (lr) {
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permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_0_L_R;
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}
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if (lx) {
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permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_0_L_F;
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}
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if (hw) {
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permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_0_H_W;
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}
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if (hr) {
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permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_0_H_R;
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}
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if (hx) {
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permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_0_H_F;
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}
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//write PERIBUS1 RTC SLOW cfg register
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DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_AHB_1_REG, reg_split_addr | permission_mask);
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return MEMP_LL_OK;
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}
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static inline void memprot_ll_peri2_rtcslow_0_get_split_sgnf_bits(bool *lw, bool *lr, bool *lx, bool *hw, bool *hr, bool *hx)
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{
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*lw = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_L_W);
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*lr = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_L_R);
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*lx = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_L_F);
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*hw = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_H_W);
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*hr = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_H_R);
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*hx = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_H_F);
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}
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static inline void memprot_ll_peri2_rtcslow_0_set_read_perm(bool lr, bool hr)
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{
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DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_L_R, lr ? 1 : 0);
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DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_H_R, hr ? 1 : 0);
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}
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static inline void memprot_ll_peri2_rtcslow_0_set_write_perm(bool lw, bool hw)
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{
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DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_L_W, lw ? 1 : 0);
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DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_H_W, hw ? 1 : 0);
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}
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static inline void memprot_ll_peri2_rtcslow_0_set_exec_perm(bool lx, bool hx)
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{
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DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_L_F, lx ? 1 : 0);
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DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_H_F, hx ? 1 : 0);
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}
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static inline uint32_t memprot_ll_peri2_rtcslow_0_get_conf_reg(void)
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{
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return DPORT_READ_PERI_REG(DPORT_PMS_PRO_DPORT_1_REG);
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}
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/**
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* ========================================================================================
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* === PeriBus2 RTC SLOW 1 (AHB1)
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* ========================================================================================
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*/
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static inline bool memprot_ll_peri2_rtcslow_1_is_intr_mine(void)
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{
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if (memprot_ll_peri2_is_assoc_intr()) {
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uint32_t faulting_address = (uint32_t)memprot_ll_peri2_rtcslow_get_fault_address();
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return faulting_address >= PERI2_RTCSLOW_1_ADDRESS_LOW && faulting_address <= PERI2_RTCSLOW_1_ADDRESS_HIGH;
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}
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return false;
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}
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static inline memprot_ll_err_t memprot_ll_peri2_rtcslow_1_set_prot(uint32_t *split_addr, bool lw, bool lr, bool lx, bool hw, bool hr, bool hx)
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{
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uint32_t addr = (uint32_t)split_addr;
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//check corresponding range fit & aligment to 32bit boundaries
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if (addr < PERI2_RTCSLOW_1_ADDRESS_LOW || addr > PERI2_RTCSLOW_1_ADDRESS_HIGH) {
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return MEMP_LL_ERR_SPLIT_ADDR_INVALID;
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}
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if (addr % 0x4 != 0) {
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return MEMP_LL_ERR_SPLIT_ADDR_UNALIGNED;
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}
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|
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uint32_t reg_split_addr = PERI2_RTCSLOW_1_ADDR_TO_CONF_REG(addr);
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|
|
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//prepare high & low permission mask
|
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uint32_t permission_mask = 0;
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if (lw) {
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permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_1_L_W;
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}
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if (lr) {
|
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permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_1_L_R;
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}
|
|
if (lx) {
|
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permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_1_L_F;
|
|
}
|
|
if (hw) {
|
|
permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_1_H_W;
|
|
}
|
|
if (hr) {
|
|
permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_1_H_R;
|
|
}
|
|
if (hx) {
|
|
permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_1_H_F;
|
|
}
|
|
|
|
//write PERIBUS1 RTC SLOW cfg register
|
|
DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_AHB_2_REG, reg_split_addr | permission_mask);
|
|
|
|
return MEMP_LL_OK;
|
|
}
|
|
|
|
static inline void memprot_ll_peri2_rtcslow_1_get_split_sgnf_bits(bool *lw, bool *lr, bool *lx, bool *hw, bool *hr, bool *hx)
|
|
{
|
|
*lw = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_L_W);
|
|
*lr = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_L_R);
|
|
*lx = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_L_F);
|
|
*hw = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_H_W);
|
|
*hr = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_H_R);
|
|
*hx = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_H_F);
|
|
}
|
|
|
|
static inline void memprot_ll_peri2_rtcslow_1_set_read_perm(bool lr, bool hr)
|
|
{
|
|
DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_L_R, lr ? 1 : 0);
|
|
DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_H_R, hr ? 1 : 0);
|
|
}
|
|
|
|
static inline void memprot_ll_peri2_rtcslow_1_set_write_perm(bool lw, bool hw)
|
|
{
|
|
DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_L_W, lw ? 1 : 0);
|
|
DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_H_W, hw ? 1 : 0);
|
|
}
|
|
|
|
static inline void memprot_ll_peri2_rtcslow_1_set_exec_perm(bool lx, bool hx)
|
|
{
|
|
DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_L_F, lx ? 1 : 0);
|
|
DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_H_F, hx ? 1 : 0);
|
|
}
|
|
|
|
static inline uint32_t memprot_ll_peri2_rtcslow_1_get_conf_reg(void)
|
|
{
|
|
return DPORT_READ_PERI_REG(DPORT_PMS_PRO_DPORT_2_REG);
|
|
}
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|