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https://github.com/espressif/esp-idf.git
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369 lines
12 KiB
C
369 lines
12 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdio.h>
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#include "esp_spi_flash.h"
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#include "soc/extmem_reg.h"
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#include "esp_private/panic_internal.h"
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#include "esp_private/panic_reason.h"
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#include "riscv/rvruntime-frames.h"
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#include "esp_private/cache_err_int.h"
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#if CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
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#if CONFIG_IDF_TARGET_ESP32C3
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#include "esp32c3/memprot.h"
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#elif CONFIG_IDF_TARGET_ESP32H2
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#include "esp32h2/memprot.h"
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#elif CONFIG_IDF_TARGET_ESP8684
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#include "esp8684/memprot.h"
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#endif
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#endif
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#if CONFIG_ESP_SYSTEM_USE_EH_FRAME
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#include "eh_frame_parser.h"
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#endif
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#define DIM(array) (sizeof(array)/sizeof(*array))
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/**
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* Structure used to define a flag/bit to test in case of cache error.
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* The message describes the cause of the error when the bit is set in
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* a given status register.
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*/
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typedef struct {
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const uint32_t bit;
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const char *msg;
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} register_bit_t;
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/**
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* Function to check each bits defined in the array reg_bits in the given
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* status register. The first bit from the array to be set in the status
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* register will have its associated message printed. This function returns
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* true. If not bit was set in the register, it returns false.
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* The order of the bits in the array is important as only the first bit to
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* be set in the register will have its associated message printed.
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*/
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static inline bool test_and_print_register_bits(const uint32_t status,
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const register_bit_t *reg_bits,
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const uint32_t size)
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{
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/* Browse the flag/bit array and test each one with the given status
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* register. */
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for (int i = 0; i < size; i++) {
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const uint32_t bit = reg_bits[i].bit;
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if ((status & bit) == bit) {
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/* Reason of the panic found, print the reason. */
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panic_print_str(reg_bits[i].msg);
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panic_print_str("\r\n");
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return true;
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}
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}
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/* Panic cause not found, no message was printed. */
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return false;
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}
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/**
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* Function called when a cache error occurs. It prints details such as the
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* explanation of why the panic occured.
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*/
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static inline void print_cache_err_details(const void *frame)
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{
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/* Define the array that contains the status (bits) to test on the register
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* EXTMEM_CORE0_ACS_CACHE_INT_ST_REG. each bit is accompanied by a small
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* message.
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* The messages have been pulled from the header file where the status bit
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* are defined. */
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const register_bit_t core0_acs_bits[] = {
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{
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.bit = EXTMEM_CORE0_DBUS_WR_ICACHE_ST,
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.msg = "dbus tried to write cache"
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},
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{
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.bit = EXTMEM_CORE0_DBUS_REJECT_ST,
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.msg = "dbus authentication failed"
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},
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{
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.bit = EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST,
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.msg = "access to cache while dbus or cache is disabled"
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},
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{
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.bit = EXTMEM_CORE0_IBUS_REJECT_ST,
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.msg = "ibus authentication failed"
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},
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{
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.bit = EXTMEM_CORE0_IBUS_WR_ICACHE_ST,
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.msg = "ibus tried to write cache"
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},
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{
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.bit = EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST,
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.msg = "access to cache while ibus or cache is disabled"
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},
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};
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/* Same goes for the register EXTMEM_CACHE_ILG_INT_ST_REG and its bits. */
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const register_bit_t cache_ilg_bits[] = {
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{
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.bit = EXTMEM_MMU_ENTRY_FAULT_ST,
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.msg = "MMU entry fault"
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},
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{
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.bit = EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST,
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.msg = "preload configurations fault"
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},
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{
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.bit = EXTMEM_ICACHE_SYNC_OP_FAULT_ST,
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.msg = "sync configurations fault"
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},
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};
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/* Read the status register EXTMEM_CORE0_ACS_CACHE_INT_ST_REG. This status
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* register is not equal to 0 when a cache access error occured. */
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const uint32_t core0_status = REG_READ(EXTMEM_CORE0_ACS_CACHE_INT_ST_REG);
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/* If the panic is due to a cache access error, one of the bit of the
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* register is set. Thus, this function will return true. */
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bool handled = test_and_print_register_bits(core0_status, core0_acs_bits, DIM(core0_acs_bits));
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/* If the panic was due to a cache illegal error, the previous call returned false and this
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* EXTMEM_CACHE_ILG_INT_ST_REG register should not me equal to 0.
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* Check each bit of it and print the message associated if found. */
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if (!handled) {
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const uint32_t cache_ilg_status = REG_READ(EXTMEM_CACHE_ILG_INT_ST_REG);
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handled = test_and_print_register_bits(cache_ilg_status, cache_ilg_bits, DIM(cache_ilg_bits));
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/* If the error was not found, print the both registers value */
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if (!handled) {
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panic_print_str("EXTMEM_CORE0_ACS_CACHE_INT_ST_REG = 0x");
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panic_print_hex(core0_status);
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panic_print_str("\r\nEXTMEM_CACHE_ILG_INT_ST_REG = 0x");
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panic_print_hex(cache_ilg_status);
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panic_print_str("\r\n");
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}
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}
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}
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/**
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* Function called when a memory protection error occurs (PMS). It prints details such as the
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* explanation of why the panic occured.
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*/
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#if CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
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static inline void print_memprot_err_details(const void *frame __attribute__((unused)))
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{
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//common memprot fault info
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mem_type_prot_t mem_type = esp_memprot_get_active_intr_memtype();
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panic_print_str( " memory type: ");
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panic_print_str( esp_memprot_mem_type_to_str(mem_type) );
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panic_print_str( "\r\n faulting address: 0x");
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panic_print_hex( esp_memprot_get_violate_addr(mem_type) );
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panic_print_str( "\r\n world:");
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panic_print_dec( esp_memprot_get_violate_world(mem_type) );
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char operation = 0;
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// IRAM fault: check instruction-fetch flag
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if ( mem_type == MEMPROT_IRAM0_SRAM ) {
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if ( esp_memprot_get_violate_loadstore(mem_type) ) {
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operation = 'X';
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}
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}
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// W/R - common
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if ( operation == 0 ) {
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operation = esp_memprot_get_violate_wr(mem_type) == MEMPROT_PMS_OP_WRITE ? 'W' : 'R';
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}
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panic_print_str( "\r\n operation type: ");
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panic_print_char( operation );
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// DRAM/DMA fault: check byte-enables
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if ( mem_type == MEMPROT_DRAM0_SRAM ) {
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panic_print_str("\r\n byte-enables: " );
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panic_print_hex(esp_memprot_get_violate_byte_en(mem_type));
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}
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panic_print_str("\r\n");
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}
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#endif
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void panic_print_registers(const void *f, int core)
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{
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uint32_t *regs = (uint32_t *)f;
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// only print ABI name
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const char *desc[] = {
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"MEPC ", "RA ", "SP ", "GP ", "TP ", "T0 ", "T1 ", "T2 ",
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"S0/FP ", "S1 ", "A0 ", "A1 ", "A2 ", "A3 ", "A4 ", "A5 ",
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"A6 ", "A7 ", "S2 ", "S3 ", "S4 ", "S5 ", "S6 ", "S7 ",
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"S8 ", "S9 ", "S10 ", "S11 ", "T3 ", "T4 ", "T5 ", "T6 ",
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"MSTATUS ", "MTVEC ", "MCAUSE ", "MTVAL ", "MHARTID "
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};
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panic_print_str("Core ");
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panic_print_dec(((RvExcFrame *)f)->mhartid);
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panic_print_str(" register dump:");
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for (int x = 0; x < sizeof(desc) / sizeof(desc[0]); x += 4) {
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panic_print_str("\r\n");
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for (int y = 0; y < 4 && x + y < sizeof(desc) / sizeof(desc[0]); y++) {
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if (desc[x + y][0] != 0) {
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panic_print_str(desc[x + y]);
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panic_print_str(": 0x");
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panic_print_hex(regs[x + y]);
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panic_print_str(" ");
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}
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}
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}
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}
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/**
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* This function will be called when a SoC-level panic occurs.
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* SoC-level panics include cache errors and watchdog interrupts.
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*/
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void panic_soc_fill_info(void *f, panic_info_t *info)
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{
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RvExcFrame *frame = (RvExcFrame *) f;
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/* Please keep in sync with PANIC_RSN_* defines */
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static const char *pseudo_reason[PANIC_RSN_COUNT] = {
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"Unknown reason",
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"Interrupt wdt timeout on CPU0",
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#if SOC_CPU_NUM > 1
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"Interrupt wdt timeout on CPU1",
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#endif
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"Cache error",
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#if CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
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"Memory protection fault",
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#endif
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};
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info->reason = pseudo_reason[0];
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info->addr = (void *) frame->mepc;
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/* The mcause has been set by the CPU when the panic occured.
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* All SoC-level panic will call this function, thus, this register
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* lets us know which error was triggered. */
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if (frame->mcause == ETS_CACHEERR_INUM) {
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/* Panic due to a cache error, multiple cache error are possible,
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* assign function print_cache_err_details to our structure's
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* details field. As its name states, it will give more details
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* about why the error happened. */
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info->core = esp_cache_err_get_cpuid();
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info->reason = pseudo_reason[PANIC_RSN_CACHEERR];
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info->details = print_cache_err_details;
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} else if (frame->mcause == ETS_T1_WDT_INUM) {
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/* Watchdog interrupt occured, get the core on which it happened
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* and update the reason/message accordingly. */
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const int core = esp_cache_err_get_cpuid();
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info->core = core;
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info->exception = PANIC_EXCEPTION_IWDT;
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#if SOC_CPU_NUM > 1
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_Static_assert(PANIC_RSN_INTWDT_CPU0 + 1 == PANIC_RSN_INTWDT_CPU1,
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"PANIC_RSN_INTWDT_CPU1 must be equal to PANIC_RSN_INTWDT_CPU0 + 1");
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#endif
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info->reason = pseudo_reason[PANIC_RSN_INTWDT_CPU0 + core];
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}
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#if CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
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else if ( frame->mcause == ETS_MEMPROT_ERR_INUM ) {
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info->core = esp_memprot_intr_get_cpuid();
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info->reason = pseudo_reason[PANIC_RSN_MEMPROT];
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info->details = print_memprot_err_details;
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}
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#endif
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}
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void panic_arch_fill_info(void *frame, panic_info_t *info)
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{
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RvExcFrame *regs = (RvExcFrame *) frame;
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info->core = 0;
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info->exception = PANIC_EXCEPTION_FAULT;
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//Please keep in sync with PANIC_RSN_* defines
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static const char *reason[] = {
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"Instruction address misaligned",
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"Instruction access fault",
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"Illegal instruction",
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"Breakpoint",
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"Load address misaligned",
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"Load access fault",
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"Store address misaligned",
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"Store access fault",
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"Environment call from U-mode",
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"Environment call from S-mode",
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NULL,
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"Environment call from M-mode",
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"Instruction page fault",
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"Load page fault",
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NULL,
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"Store page fault",
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};
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if (regs->mcause < (sizeof(reason) / sizeof(reason[0]))) {
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if (reason[regs->mcause] != NULL) {
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info->reason = (reason[regs->mcause]);
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}
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}
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info->description = "Exception was unhandled.";
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info->addr = (void *) regs->mepc;
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info->frame = ®s;
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}
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static void panic_print_basic_backtrace(const void *frame, int core) {
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// Basic backtrace
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panic_print_str("\r\nStack memory:\r\n");
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uint32_t sp = (uint32_t)((RvExcFrame *)frame)->sp;
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const int per_line = 8;
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for (int x = 0; x < 1024; x += per_line * sizeof(uint32_t)) {
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uint32_t *spp = (uint32_t *)(sp + x);
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panic_print_hex(sp + x);
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panic_print_str(": ");
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for (int y = 0; y < per_line; y++) {
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panic_print_str("0x");
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panic_print_hex(spp[y]);
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panic_print_str(y == per_line - 1 ? "\r\n" : " ");
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}
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}
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}
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void panic_print_backtrace(const void *frame, int core)
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{
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#if CONFIG_ESP_SYSTEM_USE_EH_FRAME
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if (!spi_flash_cache_enabled()) {
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panic_print_str("\r\nWarning: SPI Flash cache is disabled, cannot process eh_frame parsing. "
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"Falling back to basic backtrace.\r\n");
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panic_print_basic_backtrace(frame, core);
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} else {
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esp_eh_frame_print_backtrace(frame);
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}
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#else
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panic_print_basic_backtrace(frame, core);
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#endif
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}
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uint32_t panic_get_address(const void *f)
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{
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return ((RvExcFrame *)f)->mepc;
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}
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uint32_t panic_get_cause(const void *f)
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{
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return ((RvExcFrame *)f)->mcause;
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}
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void panic_set_address(void *f, uint32_t addr)
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{
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((RvExcFrame *)f)->mepc = addr;
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}
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