mirror of
https://github.com/espressif/esp-idf.git
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195 lines
7.7 KiB
C
195 lines
7.7 KiB
C
/*
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* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "esp_rom_sys.h"
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#include "esp_attr.h"
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#include "soc/i2c_ana_mst_reg.h"
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#include "hal/regi2c_ctrl_ll.h"
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/**
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* DIG_REG - 0x6D - BIT10
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* PLL_CPU - 0x67 - BIT11
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* PLL_SDIO - 0x62 - BIT6
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* BIAS - 0x6A - BIT12
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* MSPI_XTAL - 0x63 - BIT9
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* PLL_SYS - 0x66 - BIT5
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* PLLA - 0x6F - BIT8
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* SAR_I2C - 0x69 - BIT7
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*/
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#define REGI2C_DIG_REG_MST_SEL (BIT(10))
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#define REGI2C_PLL_CPU_MST_SEL (BIT(11))
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#define REGI2C_PLL_SDIO_MST_SEL (BIT(6))
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#define REGI2C_BIAS_MST_SEL (BIT(12))
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#define REGI2C_MSPI_XTAL_MST_SEL (BIT(9))
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#define REGI2C_PLL_SYS_MST_SEL (BIT(5))
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#define REGI2C_PLLA_MST_SEL (BIT(8))
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#define REGI2C_SAR_I2C_MST_SEL (BIT(7))
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#define I2C_ANA_MST_I2C_CTRL_REG(n) (I2C_ANA_MST_I2C0_CTRL_REG + n*4) // 0: I2C_ANA_MST_I2C0_CTRL_REG; 1: I2C_ANA_MST_I2C1_CTRL_REG
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#define REGI2C_RTC_BUSY (BIT(25))
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#define REGI2C_RTC_BUSY_M (BIT(25))
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#define REGI2C_RTC_BUSY_V 0x1
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#define REGI2C_RTC_BUSY_S 25
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#define REGI2C_RTC_WR_CNTL (BIT(24))
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#define REGI2C_RTC_WR_CNTL_M (BIT(24))
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#define REGI2C_RTC_WR_CNTL_V 0x1
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#define REGI2C_RTC_WR_CNTL_S 24
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#define REGI2C_RTC_DATA 0x000000FF
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#define REGI2C_RTC_DATA_M ((I2C_RTC_DATA_V)<<(I2C_RTC_DATA_S))
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#define REGI2C_RTC_DATA_V 0xFF
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#define REGI2C_RTC_DATA_S 16
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#define REGI2C_RTC_ADDR 0x000000FF
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#define REGI2C_RTC_ADDR_M ((I2C_RTC_ADDR_V)<<(I2C_RTC_ADDR_S))
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#define REGI2C_RTC_ADDR_V 0xFF
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#define REGI2C_RTC_ADDR_S 8
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#define REGI2C_RTC_SLAVE_ID 0x000000FF
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#define REGI2C_RTC_SLAVE_ID_M ((I2C_RTC_SLAVE_ID_V)<<(I2C_RTC_SLAVE_ID_S))
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#define REGI2C_RTC_SLAVE_ID_V 0xFF
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#define REGI2C_RTC_SLAVE_ID_S 0
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/* SLAVE */
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#define REGI2C_DIG_REG (0x6d)
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#define REGI2C_DIG_REG_HOSTID 0
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#define REGI2C_CPU_PLL (0x67)
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#define REGI2C_CPU_PLL_HOSTID 0
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#define REGI2C_SDIO_PLL (0x62)
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#define REGI2C_SDIO_PLL_HOSTID 0
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#define REGI2C_BIAS (0x6a)
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#define REGI2C_BIAS_HOSTID 0
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#define REGI2C_MSPI (0x63)
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#define REGI2C_MSPI_HOSTID 0
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#define REGI2C_SYS_PLL (0x66)
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#define REGI2C_SYS_PLL_HOSTID 0
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#define REGI2C_PLLA (0x6f)
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#define REGI2C_PLLA_HOSTID 0
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#define REGI2C_SAR_I2C (0x69)
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#define REGI2C_SAR_I2C_HOSTID 0
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/* SLAVE END */
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uint8_t esp_rom_regi2c_read(uint8_t block, uint8_t host_id, uint8_t reg_add) __attribute__((alias("regi2c_read_impl")));
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uint8_t esp_rom_regi2c_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) __attribute__((alias("regi2c_read_mask_impl")));
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void esp_rom_regi2c_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) __attribute__((alias("regi2c_write_impl")));
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void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) __attribute__((alias("regi2c_write_mask_impl")));
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static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block)
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{
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int __DECLARE_RCC_RC_ATOMIC_ENV __attribute__ ((unused)); // Right now this patch in rom can not depend on esp_hw_support, after IDF-10110 is done, this should be removed, should have spinlock protection
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regi2c_ctrl_ll_master_enable_clock(true);
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REG_SET_FIELD(I2C_ANA_MST_ANA_CONF2_REG, I2C_ANA_MST_ANA_CONF2, 0);
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REG_SET_FIELD(I2C_ANA_MST_ANA_CONF1_REG, I2C_ANA_MST_ANA_CONF1, 0);
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switch (block) {
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case REGI2C_DIG_REG:
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REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_DIG_REG_MST_SEL);
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break;
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case REGI2C_CPU_PLL:
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REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_PLL_CPU_MST_SEL);
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break;
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case REGI2C_SDIO_PLL:
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REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_PLL_SDIO_MST_SEL);
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break;
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case REGI2C_BIAS:
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REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_BIAS_MST_SEL);
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break;
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case REGI2C_MSPI:
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REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_MSPI_XTAL_MST_SEL);
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break;
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case REGI2C_SYS_PLL:
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REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_PLL_SYS_MST_SEL);
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break;
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case REGI2C_PLLA:
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REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_PLLA_MST_SEL);
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break;
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case REGI2C_SAR_I2C:
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REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_SAR_I2C_MST_SEL);
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break;
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}
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return 0;
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}
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uint8_t IRAM_ATTR regi2c_read_impl(uint8_t block, uint8_t host_id, uint8_t reg_add)
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{
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(void)host_id;
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uint8_t i2c_sel = regi2c_enable_block(block);
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while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle
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uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
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| (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S;
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REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp);
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while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
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uint8_t ret = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA);
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return ret;
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}
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uint8_t IRAM_ATTR regi2c_read_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb)
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{
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assert(msb - lsb < 8);
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uint8_t i2c_sel = regi2c_enable_block(block);
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(void)host_id;
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while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle
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uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
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| (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S;
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REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp);
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while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
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uint32_t data = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA);
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uint8_t ret = (uint8_t)((data >> lsb) & (~(0xFFFFFFFF << (msb - lsb + 1))));
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return ret;
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}
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void IRAM_ATTR regi2c_write_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data)
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{
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(void)host_id;
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uint8_t i2c_sel = regi2c_enable_block(block);
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while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle
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uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
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| ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S)
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| ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) // 0: READ I2C register; 1: Write I2C register;
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| (((uint32_t)data & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S);
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REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp);
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while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
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}
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void IRAM_ATTR regi2c_write_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data)
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{
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(void)host_id;
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assert(msb - lsb < 8);
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uint8_t i2c_sel = regi2c_enable_block(block);
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while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
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/*Read the i2c bus register*/
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uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
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| (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S;
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REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp);
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while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
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temp = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA);
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/*Write the i2c bus register*/
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temp &= ((~(0xFFFFFFFF << lsb)) | (0xFFFFFFFF << (msb + 1)));
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temp = (((uint32_t)data & (~(0xFFFFFFFF << (msb - lsb + 1)))) << lsb) | temp;
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temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
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| ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S)
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| ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S)
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| ((temp & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S);
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REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp);
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while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
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}
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