mirror of
https://github.com/espressif/esp-idf.git
synced 2024-09-20 10:46:02 -04:00
a0e3d488da
This commit enables ULP FSM support for esp32s3 and updates ULP FSM code flow for other chips. It adds C Macro support for the ULP FSM instruction set on esp32s2 and esp32s3. The unit tests are also updated to test ULP FSM on ep32s2 and esp32s3.
198 lines
7.0 KiB
C
198 lines
7.0 KiB
C
/*
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* SPDX-FileCopyrightText: 2010-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdio.h>
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#include <string.h>
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#include <stdlib.h>
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#include "sdkconfig.h"
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp_log.h"
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#if CONFIG_IDF_TARGET_ESP32
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#include "esp32/clk.h"
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#include "esp32/ulp.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/clk.h"
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#include "esp32s2/ulp.h"
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#elif CONFIG_IDF_TARGET_ESP32S3
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#include "esp32s3/clk.h"
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#include "esp32s3/ulp.h"
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#endif
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#include "soc/soc.h"
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#include "soc/rtc.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/sens_reg.h"
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#include "ulp_private.h"
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#include "esp_rom_sys.h"
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typedef struct {
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uint32_t magic;
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uint16_t text_offset;
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uint16_t text_size;
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uint16_t data_size;
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uint16_t bss_size;
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} ulp_binary_header_t;
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#define ULP_BINARY_MAGIC_ESP32 (0x00706c75)
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static const char* TAG = "ulp";
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esp_err_t ulp_run(uint32_t entry_point)
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{
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#if CONFIG_IDF_TARGET_ESP32
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// disable ULP timer
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CLEAR_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
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// wait for at least 1 RTC_SLOW_CLK cycle
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esp_rom_delay_us(10);
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// set entry point
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REG_SET_FIELD(SENS_SAR_START_FORCE_REG, SENS_PC_INIT, entry_point);
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// disable force start
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CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_FORCE_START_TOP_M);
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// set time until wakeup is allowed to the smallest possible
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REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_MIN_SLP_VAL, RTC_CNTL_MIN_SLP_VAL_MIN);
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// make sure voltage is raised when RTC 8MCLK is enabled
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SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FOLW_8M);
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SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_CORE_FOLW_8M);
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SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_SLEEP_FOLW_8M);
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// enable ULP timer
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SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
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#else
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/* Reset COCPU when power on. */
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SET_PERI_REG_MASK(RTC_CNTL_ULP_CP_CTRL_REG, RTC_CNTL_ULP_CP_RESET);
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esp_rom_delay_us(20);
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CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_CTRL_REG, RTC_CNTL_ULP_CP_RESET);
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// disable ULP timer
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CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
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// wait for at least 1 RTC_SLOW_CLK cycle
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esp_rom_delay_us(10);
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// set entry point
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REG_SET_FIELD(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_PC_INIT, entry_point);
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SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SEL); // Select ULP_TIMER trigger target for ULP.
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// start ULP clock gate.
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SET_PERI_REG_MASK(RTC_CNTL_ULP_CP_CTRL_REG ,RTC_CNTL_ULP_CP_CLK_FO);
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// ULP FSM sends the DONE signal.
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CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE_FORCE);
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#if CONFIG_IDF_TARGET_ESP32S3
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/* Set the CLKGATE_EN signal on esp32s3 */
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SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_CLKGATE_EN);
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#endif
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/* Clear interrupt COCPU status */
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REG_WRITE(RTC_CNTL_INT_CLR_REG, RTC_CNTL_COCPU_INT_CLR | RTC_CNTL_COCPU_TRAP_INT_CLR | RTC_CNTL_ULP_CP_INT_CLR);
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// 1: start with timer. wait ULP_TIMER cnt timer.
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CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_CTRL_REG, RTC_CNTL_ULP_CP_FORCE_START_TOP); // Select ULP_TIMER timer as COCPU trigger source
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SET_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN); // Software to turn on the ULP_TIMER timer
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#endif
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return ESP_OK;
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}
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esp_err_t ulp_load_binary(uint32_t load_addr, const uint8_t* program_binary, size_t program_size)
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{
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size_t program_size_bytes = program_size * sizeof(uint32_t);
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size_t load_addr_bytes = load_addr * sizeof(uint32_t);
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if (program_size_bytes < sizeof(ulp_binary_header_t)) {
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return ESP_ERR_INVALID_SIZE;
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}
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if (load_addr_bytes > ULP_RESERVE_MEM) {
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return ESP_ERR_INVALID_ARG;
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}
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if (load_addr_bytes + program_size_bytes > ULP_RESERVE_MEM) {
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return ESP_ERR_INVALID_SIZE;
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}
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// Make a copy of a header in case program_binary isn't aligned
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ulp_binary_header_t header;
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memcpy(&header, program_binary, sizeof(header));
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if (header.magic != ULP_BINARY_MAGIC_ESP32) {
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return ESP_ERR_NOT_SUPPORTED;
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}
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size_t total_size = (size_t) header.text_offset + (size_t) header.text_size +
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(size_t) header.data_size;
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ESP_LOGD(TAG, "program_size_bytes: %d total_size: %d offset: %d .text: %d, .data: %d, .bss: %d",
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program_size_bytes, total_size, header.text_offset,
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header.text_size, header.data_size, header.bss_size);
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if (total_size != program_size_bytes) {
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return ESP_ERR_INVALID_SIZE;
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}
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size_t text_data_size = header.text_size + header.data_size;
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uint8_t* base = (uint8_t*) RTC_SLOW_MEM;
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memcpy(base + load_addr_bytes, program_binary + header.text_offset, text_data_size);
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memset(base + load_addr_bytes + text_data_size, 0, header.bss_size);
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return ESP_OK;
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}
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esp_err_t ulp_set_wakeup_period(size_t period_index, uint32_t period_us)
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{
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#if CONFIG_IDF_TARGET_ESP32
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if (period_index > 4) {
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return ESP_ERR_INVALID_ARG;
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}
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uint64_t period_us_64 = period_us;
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uint64_t period_cycles = (period_us_64 << RTC_CLK_CAL_FRACT) / esp_clk_slowclk_cal_get();
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uint64_t min_sleep_period_cycles = ULP_FSM_PREPARE_SLEEP_CYCLES
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+ ULP_FSM_WAKEUP_SLEEP_CYCLES
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+ REG_GET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT);
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if (period_cycles < min_sleep_period_cycles) {
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period_cycles = 0;
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ESP_LOGW(TAG, "Sleep period clipped to minimum of %d cycles", (uint32_t) min_sleep_period_cycles);
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} else {
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period_cycles -= min_sleep_period_cycles;
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}
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REG_SET_FIELD(SENS_ULP_CP_SLEEP_CYC0_REG + period_index * sizeof(uint32_t),
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SENS_SLEEP_CYCLES_S0, (uint32_t) period_cycles);
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#elif defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3)
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if (period_index > 4) {
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return ESP_ERR_INVALID_ARG;
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}
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uint64_t period_us_64 = period_us;
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rtc_slow_freq_t slow_clk_freq = rtc_clk_slow_freq_get();
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rtc_slow_freq_t rtc_slow_freq_x32k = RTC_SLOW_FREQ_32K_XTAL;
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rtc_slow_freq_t rtc_slow_freq_8MD256 = RTC_SLOW_FREQ_8MD256;
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rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX;
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if (slow_clk_freq == (rtc_slow_freq_x32k)) {
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cal_clk = RTC_CAL_32K_XTAL;
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} else if (slow_clk_freq == rtc_slow_freq_8MD256) {
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cal_clk = RTC_CAL_8MD256;
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}
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uint32_t slow_clk_period = rtc_clk_cal(cal_clk, 100);
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uint64_t period_cycles = rtc_time_us_to_slowclk(period_us_64, slow_clk_period);
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REG_SET_FIELD(RTC_CNTL_ULP_CP_TIMER_1_REG, RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE, ((uint32_t)period_cycles));
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#endif
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return ESP_OK;
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}
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void ulp_timer_stop(void)
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{
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#if CONFIG_IDF_TARGET_ESP32
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CLEAR_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
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#else
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CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
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#endif
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}
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void ulp_timer_resume(void)
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{
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#if CONFIG_IDF_TARGET_ESP32
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SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
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#else
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SET_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
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#endif
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}
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