mirror of
https://github.com/espressif/esp-idf.git
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337 lines
12 KiB
C
337 lines
12 KiB
C
/**
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** LPPERI_CLK_EN_REG register
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* need_des
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*/
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#define LPPERI_CLK_EN_REG (DR_REG_LPPERI_BASE + 0x0)
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/** LPPERI_RNG_CK_EN : R/W; bitpos: [24]; default: 1;
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* need_des
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*/
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#define LPPERI_RNG_CK_EN (BIT(24))
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#define LPPERI_RNG_CK_EN_M (LPPERI_RNG_CK_EN_V << LPPERI_RNG_CK_EN_S)
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#define LPPERI_RNG_CK_EN_V 0x00000001U
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#define LPPERI_RNG_CK_EN_S 24
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/** LPPERI_OTP_DBG_CK_EN : R/W; bitpos: [25]; default: 1;
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* need_des
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*/
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#define LPPERI_OTP_DBG_CK_EN (BIT(25))
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#define LPPERI_OTP_DBG_CK_EN_M (LPPERI_OTP_DBG_CK_EN_V << LPPERI_OTP_DBG_CK_EN_S)
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#define LPPERI_OTP_DBG_CK_EN_V 0x00000001U
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#define LPPERI_OTP_DBG_CK_EN_S 25
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/** LPPERI_LP_UART_CK_EN : R/W; bitpos: [26]; default: 1;
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* need_des
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*/
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#define LPPERI_LP_UART_CK_EN (BIT(26))
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#define LPPERI_LP_UART_CK_EN_M (LPPERI_LP_UART_CK_EN_V << LPPERI_LP_UART_CK_EN_S)
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#define LPPERI_LP_UART_CK_EN_V 0x00000001U
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#define LPPERI_LP_UART_CK_EN_S 26
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/** LPPERI_LP_IO_CK_EN : R/W; bitpos: [27]; default: 1;
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* need_des
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*/
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#define LPPERI_LP_IO_CK_EN (BIT(27))
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#define LPPERI_LP_IO_CK_EN_M (LPPERI_LP_IO_CK_EN_V << LPPERI_LP_IO_CK_EN_S)
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#define LPPERI_LP_IO_CK_EN_V 0x00000001U
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#define LPPERI_LP_IO_CK_EN_S 27
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/** LPPERI_LP_EXT_I2C_CK_EN : R/W; bitpos: [28]; default: 1;
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* need_des
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*/
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#define LPPERI_LP_EXT_I2C_CK_EN (BIT(28))
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#define LPPERI_LP_EXT_I2C_CK_EN_M (LPPERI_LP_EXT_I2C_CK_EN_V << LPPERI_LP_EXT_I2C_CK_EN_S)
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#define LPPERI_LP_EXT_I2C_CK_EN_V 0x00000001U
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#define LPPERI_LP_EXT_I2C_CK_EN_S 28
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/** LPPERI_LP_ANA_I2C_CK_EN : R/W; bitpos: [29]; default: 1;
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* need_des
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*/
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#define LPPERI_LP_ANA_I2C_CK_EN (BIT(29))
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#define LPPERI_LP_ANA_I2C_CK_EN_M (LPPERI_LP_ANA_I2C_CK_EN_V << LPPERI_LP_ANA_I2C_CK_EN_S)
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#define LPPERI_LP_ANA_I2C_CK_EN_V 0x00000001U
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#define LPPERI_LP_ANA_I2C_CK_EN_S 29
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/** LPPERI_EFUSE_CK_EN : R/W; bitpos: [30]; default: 1;
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* need_des
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*/
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#define LPPERI_EFUSE_CK_EN (BIT(30))
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#define LPPERI_EFUSE_CK_EN_M (LPPERI_EFUSE_CK_EN_V << LPPERI_EFUSE_CK_EN_S)
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#define LPPERI_EFUSE_CK_EN_V 0x00000001U
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#define LPPERI_EFUSE_CK_EN_S 30
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/** LPPERI_LP_CPU_CK_EN : R/W; bitpos: [31]; default: 0;
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* need_des
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*/
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#define LPPERI_LP_CPU_CK_EN (BIT(31))
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#define LPPERI_LP_CPU_CK_EN_M (LPPERI_LP_CPU_CK_EN_V << LPPERI_LP_CPU_CK_EN_S)
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#define LPPERI_LP_CPU_CK_EN_V 0x00000001U
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#define LPPERI_LP_CPU_CK_EN_S 31
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/** LPPERI_RESET_EN_REG register
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* need_des
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*/
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#define LPPERI_RESET_EN_REG (DR_REG_LPPERI_BASE + 0x4)
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/** LPPERI_BUS_RESET_EN : WT; bitpos: [23]; default: 0;
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* need_des
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*/
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#define LPPERI_BUS_RESET_EN (BIT(23))
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#define LPPERI_BUS_RESET_EN_M (LPPERI_BUS_RESET_EN_V << LPPERI_BUS_RESET_EN_S)
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#define LPPERI_BUS_RESET_EN_V 0x00000001U
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#define LPPERI_BUS_RESET_EN_S 23
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/** LPPERI_LP_BLE_TIMER_RESET_EN : R/W; bitpos: [24]; default: 0;
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* need_des
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*/
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#define LPPERI_LP_BLE_TIMER_RESET_EN (BIT(24))
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#define LPPERI_LP_BLE_TIMER_RESET_EN_M (LPPERI_LP_BLE_TIMER_RESET_EN_V << LPPERI_LP_BLE_TIMER_RESET_EN_S)
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#define LPPERI_LP_BLE_TIMER_RESET_EN_V 0x00000001U
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#define LPPERI_LP_BLE_TIMER_RESET_EN_S 24
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/** LPPERI_OTP_DBG_RESET_EN : R/W; bitpos: [25]; default: 0;
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* need_des
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*/
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#define LPPERI_OTP_DBG_RESET_EN (BIT(25))
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#define LPPERI_OTP_DBG_RESET_EN_M (LPPERI_OTP_DBG_RESET_EN_V << LPPERI_OTP_DBG_RESET_EN_S)
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#define LPPERI_OTP_DBG_RESET_EN_V 0x00000001U
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#define LPPERI_OTP_DBG_RESET_EN_S 25
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/** LPPERI_LP_UART_RESET_EN : R/W; bitpos: [26]; default: 0;
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* need_des
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*/
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#define LPPERI_LP_UART_RESET_EN (BIT(26))
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#define LPPERI_LP_UART_RESET_EN_M (LPPERI_LP_UART_RESET_EN_V << LPPERI_LP_UART_RESET_EN_S)
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#define LPPERI_LP_UART_RESET_EN_V 0x00000001U
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#define LPPERI_LP_UART_RESET_EN_S 26
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/** LPPERI_LP_IO_RESET_EN : R/W; bitpos: [27]; default: 0;
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* need_des
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*/
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#define LPPERI_LP_IO_RESET_EN (BIT(27))
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#define LPPERI_LP_IO_RESET_EN_M (LPPERI_LP_IO_RESET_EN_V << LPPERI_LP_IO_RESET_EN_S)
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#define LPPERI_LP_IO_RESET_EN_V 0x00000001U
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#define LPPERI_LP_IO_RESET_EN_S 27
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/** LPPERI_LP_EXT_I2C_RESET_EN : R/W; bitpos: [28]; default: 0;
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* need_des
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*/
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#define LPPERI_LP_EXT_I2C_RESET_EN (BIT(28))
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#define LPPERI_LP_EXT_I2C_RESET_EN_M (LPPERI_LP_EXT_I2C_RESET_EN_V << LPPERI_LP_EXT_I2C_RESET_EN_S)
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#define LPPERI_LP_EXT_I2C_RESET_EN_V 0x00000001U
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#define LPPERI_LP_EXT_I2C_RESET_EN_S 28
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/** LPPERI_LP_ANA_I2C_RESET_EN : R/W; bitpos: [29]; default: 0;
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* need_des
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*/
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#define LPPERI_LP_ANA_I2C_RESET_EN (BIT(29))
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#define LPPERI_LP_ANA_I2C_RESET_EN_M (LPPERI_LP_ANA_I2C_RESET_EN_V << LPPERI_LP_ANA_I2C_RESET_EN_S)
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#define LPPERI_LP_ANA_I2C_RESET_EN_V 0x00000001U
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#define LPPERI_LP_ANA_I2C_RESET_EN_S 29
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/** LPPERI_EFUSE_RESET_EN : R/W; bitpos: [30]; default: 0;
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* need_des
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*/
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#define LPPERI_EFUSE_RESET_EN (BIT(30))
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#define LPPERI_EFUSE_RESET_EN_M (LPPERI_EFUSE_RESET_EN_V << LPPERI_EFUSE_RESET_EN_S)
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#define LPPERI_EFUSE_RESET_EN_V 0x00000001U
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#define LPPERI_EFUSE_RESET_EN_S 30
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/** LPPERI_LP_CPU_RESET_EN : WT; bitpos: [31]; default: 0;
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* need_des
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*/
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#define LPPERI_LP_CPU_RESET_EN (BIT(31))
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#define LPPERI_LP_CPU_RESET_EN_M (LPPERI_LP_CPU_RESET_EN_V << LPPERI_LP_CPU_RESET_EN_S)
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#define LPPERI_LP_CPU_RESET_EN_V 0x00000001U
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#define LPPERI_LP_CPU_RESET_EN_S 31
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/** LPPERI_RNG_DATA_REG register
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* need_des
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*/
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#define LPPERI_RNG_DATA_REG (DR_REG_LPPERI_BASE + 0x8)
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/** LPPERI_RNG_DATA : RO; bitpos: [31:0]; default: 0;
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* need_des
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*/
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#define LPPERI_RNG_DATA 0xFFFFFFFFU
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#define LPPERI_RNG_DATA_M (LPPERI_RNG_DATA_V << LPPERI_RNG_DATA_S)
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#define LPPERI_RNG_DATA_V 0xFFFFFFFFU
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#define LPPERI_RNG_DATA_S 0
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/** LPPERI_CPU_REG register
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* need_des
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*/
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#define LPPERI_CPU_REG (DR_REG_LPPERI_BASE + 0xc)
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/** LPPERI_LPCORE_DBGM_UNAVALIABLE : R/W; bitpos: [31]; default: 1;
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* need_des
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*/
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#define LPPERI_LPCORE_DBGM_UNAVALIABLE (BIT(31))
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#define LPPERI_LPCORE_DBGM_UNAVALIABLE_M (LPPERI_LPCORE_DBGM_UNAVALIABLE_V << LPPERI_LPCORE_DBGM_UNAVALIABLE_S)
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#define LPPERI_LPCORE_DBGM_UNAVALIABLE_V 0x00000001U
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#define LPPERI_LPCORE_DBGM_UNAVALIABLE_S 31
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/** LPPERI_BUS_TIMEOUT_REG register
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* need_des
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*/
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#define LPPERI_BUS_TIMEOUT_REG (DR_REG_LPPERI_BASE + 0x10)
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/** LPPERI_LP_PERI_TIMEOUT_THRES : R/W; bitpos: [29:14]; default: 65535;
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* need_des
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*/
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#define LPPERI_LP_PERI_TIMEOUT_THRES 0x0000FFFFU
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#define LPPERI_LP_PERI_TIMEOUT_THRES_M (LPPERI_LP_PERI_TIMEOUT_THRES_V << LPPERI_LP_PERI_TIMEOUT_THRES_S)
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#define LPPERI_LP_PERI_TIMEOUT_THRES_V 0x0000FFFFU
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#define LPPERI_LP_PERI_TIMEOUT_THRES_S 14
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/** LPPERI_LP_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [30]; default: 0;
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* need_des
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*/
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#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR (BIT(30))
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#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_M (LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_V << LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_S)
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#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U
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#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_S 30
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/** LPPERI_LP_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [31]; default: 1;
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* need_des
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*/
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#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN (BIT(31))
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#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_M (LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_V << LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_S)
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#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U
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#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_S 31
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/** LPPERI_BUS_TIMEOUT_ADDR_REG register
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* need_des
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*/
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#define LPPERI_BUS_TIMEOUT_ADDR_REG (DR_REG_LPPERI_BASE + 0x14)
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/** LPPERI_LP_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
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* need_des
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*/
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#define LPPERI_LP_PERI_TIMEOUT_ADDR 0xFFFFFFFFU
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#define LPPERI_LP_PERI_TIMEOUT_ADDR_M (LPPERI_LP_PERI_TIMEOUT_ADDR_V << LPPERI_LP_PERI_TIMEOUT_ADDR_S)
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#define LPPERI_LP_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU
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#define LPPERI_LP_PERI_TIMEOUT_ADDR_S 0
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/** LPPERI_BUS_TIMEOUT_UID_REG register
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* need_des
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*/
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#define LPPERI_BUS_TIMEOUT_UID_REG (DR_REG_LPPERI_BASE + 0x18)
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/** LPPERI_LP_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
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* need_des
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*/
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#define LPPERI_LP_PERI_TIMEOUT_UID 0x0000007FU
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#define LPPERI_LP_PERI_TIMEOUT_UID_M (LPPERI_LP_PERI_TIMEOUT_UID_V << LPPERI_LP_PERI_TIMEOUT_UID_S)
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#define LPPERI_LP_PERI_TIMEOUT_UID_V 0x0000007FU
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#define LPPERI_LP_PERI_TIMEOUT_UID_S 0
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/** LPPERI_MEM_CTRL_REG register
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* need_des
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*/
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#define LPPERI_MEM_CTRL_REG (DR_REG_LPPERI_BASE + 0x1c)
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/** LPPERI_UART_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0;
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* need_des
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*/
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#define LPPERI_UART_WAKEUP_FLAG_CLR (BIT(0))
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#define LPPERI_UART_WAKEUP_FLAG_CLR_M (LPPERI_UART_WAKEUP_FLAG_CLR_V << LPPERI_UART_WAKEUP_FLAG_CLR_S)
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#define LPPERI_UART_WAKEUP_FLAG_CLR_V 0x00000001U
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#define LPPERI_UART_WAKEUP_FLAG_CLR_S 0
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/** LPPERI_UART_WAKEUP_FLAG : R/WTC/SS; bitpos: [1]; default: 0;
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* need_des
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*/
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#define LPPERI_UART_WAKEUP_FLAG (BIT(1))
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#define LPPERI_UART_WAKEUP_FLAG_M (LPPERI_UART_WAKEUP_FLAG_V << LPPERI_UART_WAKEUP_FLAG_S)
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#define LPPERI_UART_WAKEUP_FLAG_V 0x00000001U
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#define LPPERI_UART_WAKEUP_FLAG_S 1
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/** LPPERI_UART_WAKEUP_EN : R/W; bitpos: [29]; default: 0;
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* need_des
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*/
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#define LPPERI_UART_WAKEUP_EN (BIT(29))
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#define LPPERI_UART_WAKEUP_EN_M (LPPERI_UART_WAKEUP_EN_V << LPPERI_UART_WAKEUP_EN_S)
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#define LPPERI_UART_WAKEUP_EN_V 0x00000001U
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#define LPPERI_UART_WAKEUP_EN_S 29
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/** LPPERI_UART_MEM_FORCE_PD : R/W; bitpos: [30]; default: 0;
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* need_des
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*/
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#define LPPERI_UART_MEM_FORCE_PD (BIT(30))
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#define LPPERI_UART_MEM_FORCE_PD_M (LPPERI_UART_MEM_FORCE_PD_V << LPPERI_UART_MEM_FORCE_PD_S)
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#define LPPERI_UART_MEM_FORCE_PD_V 0x00000001U
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#define LPPERI_UART_MEM_FORCE_PD_S 30
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/** LPPERI_UART_MEM_FORCE_PU : R/W; bitpos: [31]; default: 1;
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* need_des
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*/
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#define LPPERI_UART_MEM_FORCE_PU (BIT(31))
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#define LPPERI_UART_MEM_FORCE_PU_M (LPPERI_UART_MEM_FORCE_PU_V << LPPERI_UART_MEM_FORCE_PU_S)
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#define LPPERI_UART_MEM_FORCE_PU_V 0x00000001U
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#define LPPERI_UART_MEM_FORCE_PU_S 31
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/** LPPERI_INTERRUPT_SOURCE_REG register
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* need_des
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*/
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#define LPPERI_INTERRUPT_SOURCE_REG (DR_REG_LPPERI_BASE + 0x20)
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/** LPPERI_LP_INTERRUPT_SOURCE : RO; bitpos: [5:0]; default: 0;
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* BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int,
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* lp_io_int
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*/
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#define LPPERI_LP_INTERRUPT_SOURCE 0x0000003FU
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#define LPPERI_LP_INTERRUPT_SOURCE_M (LPPERI_LP_INTERRUPT_SOURCE_V << LPPERI_LP_INTERRUPT_SOURCE_S)
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#define LPPERI_LP_INTERRUPT_SOURCE_V 0x0000003FU
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#define LPPERI_LP_INTERRUPT_SOURCE_S 0
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/** LPPERI_DEBUG_SEL0_REG register
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* need des
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*/
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#define LPPERI_DEBUG_SEL0_REG (DR_REG_LPPERI_BASE + 0x24)
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/** LPPERI_DEBUG_SEL0 : R/W; bitpos: [6:0]; default: 0;
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* need des
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*/
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#define LPPERI_DEBUG_SEL0 0x0000007FU
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#define LPPERI_DEBUG_SEL0_M (LPPERI_DEBUG_SEL0_V << LPPERI_DEBUG_SEL0_S)
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#define LPPERI_DEBUG_SEL0_V 0x0000007FU
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#define LPPERI_DEBUG_SEL0_S 0
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/** LPPERI_DEBUG_SEL1 : R/W; bitpos: [13:7]; default: 0;
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* need des
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*/
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#define LPPERI_DEBUG_SEL1 0x0000007FU
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#define LPPERI_DEBUG_SEL1_M (LPPERI_DEBUG_SEL1_V << LPPERI_DEBUG_SEL1_S)
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#define LPPERI_DEBUG_SEL1_V 0x0000007FU
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#define LPPERI_DEBUG_SEL1_S 7
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/** LPPERI_DEBUG_SEL2 : R/W; bitpos: [20:14]; default: 0;
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* need des
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*/
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#define LPPERI_DEBUG_SEL2 0x0000007FU
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#define LPPERI_DEBUG_SEL2_M (LPPERI_DEBUG_SEL2_V << LPPERI_DEBUG_SEL2_S)
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#define LPPERI_DEBUG_SEL2_V 0x0000007FU
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#define LPPERI_DEBUG_SEL2_S 14
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/** LPPERI_DEBUG_SEL3 : R/W; bitpos: [27:21]; default: 0;
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* need des
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*/
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#define LPPERI_DEBUG_SEL3 0x0000007FU
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#define LPPERI_DEBUG_SEL3_M (LPPERI_DEBUG_SEL3_V << LPPERI_DEBUG_SEL3_S)
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#define LPPERI_DEBUG_SEL3_V 0x0000007FU
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#define LPPERI_DEBUG_SEL3_S 21
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/** LPPERI_DEBUG_SEL1_REG register
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* need des
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*/
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#define LPPERI_DEBUG_SEL1_REG (DR_REG_LPPERI_BASE + 0x28)
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/** LPPERI_DEBUG_SEL4 : R/W; bitpos: [6:0]; default: 0;
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* need des
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*/
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#define LPPERI_DEBUG_SEL4 0x0000007FU
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#define LPPERI_DEBUG_SEL4_M (LPPERI_DEBUG_SEL4_V << LPPERI_DEBUG_SEL4_S)
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#define LPPERI_DEBUG_SEL4_V 0x0000007FU
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#define LPPERI_DEBUG_SEL4_S 0
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/** LPPERI_DATE_REG register
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* need_des
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*/
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#define LPPERI_DATE_REG (DR_REG_LPPERI_BASE + 0x3fc)
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/** LPPERI_LPPERI_DATE : R/W; bitpos: [30:0]; default: 35676464;
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* need_des
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*/
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#define LPPERI_LPPERI_DATE 0x7FFFFFFFU
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#define LPPERI_LPPERI_DATE_M (LPPERI_LPPERI_DATE_V << LPPERI_LPPERI_DATE_S)
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#define LPPERI_LPPERI_DATE_V 0x7FFFFFFFU
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#define LPPERI_LPPERI_DATE_S 0
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/** LPPERI_CLK_EN : R/W; bitpos: [31]; default: 0;
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* need_des
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*/
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#define LPPERI_CLK_EN (BIT(31))
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#define LPPERI_CLK_EN_M (LPPERI_CLK_EN_V << LPPERI_CLK_EN_S)
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#define LPPERI_CLK_EN_V 0x00000001U
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#define LPPERI_CLK_EN_S 31
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#ifdef __cplusplus
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}
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#endif
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