mirror of
https://github.com/espressif/esp-idf.git
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127 lines
3.5 KiB
C
127 lines
3.5 KiB
C
/*
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* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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#include <sys/param.h>
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#include "soc/soc_caps.h"
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#include "hal/assert.h"
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#include "hal/efuse_hal.h"
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#include "hal/efuse_ll.h"
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#include "esp32s2/rom/efuse.h"
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#include "esp_attr.h"
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#define ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block) ((error_reg) & (0x0F << (4 * (block))))
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IRAM_ATTR uint32_t efuse_hal_get_major_chip_version(void)
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{
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return efuse_ll_get_chip_wafer_version_major();
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}
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IRAM_ATTR uint32_t efuse_hal_get_minor_chip_version(void)
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{
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return efuse_ll_get_chip_wafer_version_minor();
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}
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/******************* eFuse control functions *************************/
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void efuse_hal_set_timing(uint32_t apb_freq_hz)
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{
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uint32_t tsup_a;
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uint32_t tpgm;
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uint32_t thp_a;
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uint32_t tpgm_inact;
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uint32_t clk_div;
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uint32_t power_on;
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uint32_t power_off;
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uint32_t tsur_a;
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uint32_t trd;
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uint32_t thr_a;
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if (apb_freq_hz == 80000000) {
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tsup_a = 0x2;
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tpgm = 0x320;
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thp_a = 0x2;
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tpgm_inact = 0x4;
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clk_div = 0xA0;
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power_on = 0xA200;
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power_off = 0x100;
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tsur_a = 0x2;
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trd = 0x4;
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thr_a = 0x2;
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} else if (apb_freq_hz == 40000000) {
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tsup_a = 0x1;
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tpgm = 0x190;
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thp_a = 0x1;
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tpgm_inact = 0x2;
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clk_div = 0x50;
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power_on = 0x5100;
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power_off = 0x80;
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tsur_a = 0x1;
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trd = 0x2;
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thr_a = 0x1;
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} else { // 20000000 or 5000000 or 10000000
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tsup_a = 0x1;
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tpgm = 0xC8;
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thp_a = 0x1;
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tpgm_inact = 0x1;
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clk_div = 0x28;
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power_on = 0x2880;
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power_off = 0x40;
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tsur_a = 0x1;
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trd = 0x1;
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thr_a = 0x1;
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}
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REG_SET_FIELD(EFUSE_WR_TIM_CONF1_REG, EFUSE_TSUP_A, tsup_a);
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REG_SET_FIELD(EFUSE_WR_TIM_CONF0_REG, EFUSE_TPGM, tpgm);
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REG_SET_FIELD(EFUSE_WR_TIM_CONF0_REG, EFUSE_THP_A, thp_a);
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REG_SET_FIELD(EFUSE_WR_TIM_CONF0_REG, EFUSE_TPGM_INACTIVE, tpgm_inact);
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REG_SET_FIELD(EFUSE_DAC_CONF_REG, EFUSE_DAC_CLK_DIV, clk_div);
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REG_SET_FIELD(EFUSE_WR_TIM_CONF1_REG, EFUSE_PWR_ON_NUM, power_on);
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REG_SET_FIELD(EFUSE_WR_TIM_CONF2_REG, EFUSE_PWR_OFF_NUM, power_off);
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REG_SET_FIELD(EFUSE_RD_TIM_CONF_REG, EFUSE_TSUR_A, tsur_a);
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REG_SET_FIELD(EFUSE_RD_TIM_CONF_REG, EFUSE_TRD, trd);
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REG_SET_FIELD(EFUSE_RD_TIM_CONF_REG, EFUSE_THR_A, thr_a);
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}
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void efuse_hal_read(void)
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{
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ets_efuse_read();
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}
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void efuse_hal_clear_program_registers(void)
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{
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ets_efuse_clear_program_registers();
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}
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void efuse_hal_program(uint32_t block)
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{
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ets_efuse_program(block);
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}
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void efuse_hal_rs_calculate(const void *data, void *rs_values)
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{
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ets_efuse_rs_calculate(data, rs_values);
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}
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/******************* eFuse control functions *************************/
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bool efuse_hal_is_coding_error_in_block(unsigned block)
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{
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if (block == 0) {
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for (unsigned i = 0; i < 5; i++) {
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if (REG_READ(EFUSE_RD_REPEAT_ERR0_REG + i * 4)) {
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return true;
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}
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}
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} else if (block <= 10) {
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// EFUSE_RD_RS_ERR0_REG: (hi) BLOCK8, BLOCK7, BLOCK6, BLOCK5, BLOCK4, BLOCK3, BLOCK2, BLOCK1 (low)
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// EFUSE_RD_RS_ERR1_REG: BLOCK10, BLOCK9
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block--;
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uint32_t error_reg = REG_READ(EFUSE_RD_RS_ERR0_REG + (block / 8) * 4);
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return ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block % 8) != 0;
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}
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return false;
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}
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