mirror of
https://github.com/espressif/esp-idf.git
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387 lines
10 KiB
C
387 lines
10 KiB
C
/**
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* \brief AES block cipher, ESP32 hardware accelerated version
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* Based on mbedTLS FIPS-197 compliant version.
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*
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* Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
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* Additions Copyright (C) 2016-2017, Espressif Systems (Shanghai) PTE Ltd
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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*/
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/*
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* The AES block cipher was designed by Vincent Rijmen and Joan Daemen.
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*
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* http://csrc.nist.gov/encryption/aes/rijndael/Rijndael.pdf
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* http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf
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*/
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#include <string.h>
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#include "mbedtls/aes.h"
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#include "hwcrypto/aes.h"
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#include "soc/dport_reg.h"
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#include "soc/hwcrypto_reg.h"
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#include <sys/lock.h>
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#include <freertos/FreeRTOS.h>
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#include "soc/cpu.h"
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#include <stdio.h>
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/* AES uses a spinlock mux not a lock as the underlying block operation
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only takes 208 cycles (to write key & compute block), +600 cycles
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for DPORT protection but +3400 cycles again if you use a full sized lock.
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For CBC, CFB, etc. this may mean that interrupts are disabled for a longer
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period of time for bigger lengths. However at the moment this has to happen
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anyway due to DPORT protection...
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*/
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static portMUX_TYPE aes_spinlock = portMUX_INITIALIZER_UNLOCKED;
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void esp_aes_acquire_hardware( void )
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{
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/* newlib locks lazy initialize on ESP-IDF */
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portENTER_CRITICAL(&aes_spinlock);
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DPORT_STALL_OTHER_CPU_START();
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{
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/* Enable AES hardware */
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_DPORT_REG_SET_BIT(DPORT_PERI_CLK_EN_REG, DPORT_PERI_EN_AES);
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/* Clear reset on digital signature & secure boot units,
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otherwise AES unit is held in reset also. */
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_DPORT_REG_CLR_BIT(DPORT_PERI_RST_EN_REG,
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DPORT_PERI_EN_AES
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| DPORT_PERI_EN_DIGITAL_SIGNATURE
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| DPORT_PERI_EN_SECUREBOOT);
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}
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DPORT_STALL_OTHER_CPU_END();
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}
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void esp_aes_release_hardware( void )
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{
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DPORT_STALL_OTHER_CPU_START();
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{
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/* Disable AES hardware */
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_DPORT_REG_SET_BIT(DPORT_PERI_RST_EN_REG, DPORT_PERI_EN_AES);
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/* Don't return other units to reset, as this pulls
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reset on RSA & SHA units, respectively. */
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_DPORT_REG_CLR_BIT(DPORT_PERI_CLK_EN_REG, DPORT_PERI_EN_AES);
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}
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DPORT_STALL_OTHER_CPU_END();
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portEXIT_CRITICAL(&aes_spinlock);
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}
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void esp_aes_init( esp_aes_context *ctx )
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{
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bzero( ctx, sizeof( esp_aes_context ) );
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}
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void esp_aes_free( esp_aes_context *ctx )
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{
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if ( ctx == NULL ) {
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return;
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}
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bzero( ctx, sizeof( esp_aes_context ) );
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}
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/*
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* AES key schedule (same for encryption or decryption, as hardware handles schedule)
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*
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*/
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int esp_aes_setkey( esp_aes_context *ctx, const unsigned char *key,
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unsigned int keybits )
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{
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if (keybits != 128 && keybits != 192 && keybits != 256) {
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return MBEDTLS_ERR_AES_INVALID_KEY_LENGTH;
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}
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ctx->key_bytes = keybits / 8;
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memcpy(ctx->key, key, ctx->key_bytes);
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return 0;
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}
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/*
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* Helper function to copy key from esp_aes_context buffer
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* to hardware key registers.
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*
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* Call only while holding esp_aes_acquire_hardware().
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*/
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static inline void esp_aes_setkey_hardware( esp_aes_context *ctx, int mode)
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{
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const uint32_t MODE_DECRYPT_BIT = 4;
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unsigned mode_reg_base = (mode == ESP_AES_ENCRYPT) ? 0 : MODE_DECRYPT_BIT;
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memcpy((uint32_t *)AES_KEY_BASE, ctx->key, ctx->key_bytes);
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DPORT_REG_WRITE(AES_MODE_REG, mode_reg_base + ((ctx->key_bytes / 8) - 2));
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}
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/* Run a single 16 byte block of AES, using the hardware engine.
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*
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* Call only while holding esp_aes_acquire_hardware().
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*/
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static inline void esp_aes_block(const void *input, void *output)
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{
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const uint32_t *input_words = (const uint32_t *)input;
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uint32_t *output_words = (uint32_t *)output;
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uint32_t *mem_block = (uint32_t *)AES_TEXT_BASE;
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for(int i = 0; i < 4; i++) {
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mem_block[i] = input_words[i];
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}
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DPORT_REG_WRITE(AES_START_REG, 1);
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DPORT_STALL_OTHER_CPU_START();
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{
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while (_DPORT_REG_READ(AES_IDLE_REG) != 1) { }
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for (int i = 0; i < 4; i++) {
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output_words[i] = mem_block[i];
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}
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}
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DPORT_STALL_OTHER_CPU_END();
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}
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/*
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* AES-ECB block encryption
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*/
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void esp_aes_encrypt( esp_aes_context *ctx,
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const unsigned char input[16],
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unsigned char output[16] )
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{
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esp_aes_acquire_hardware();
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esp_aes_setkey_hardware(ctx, ESP_AES_ENCRYPT);
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esp_aes_block(input, output);
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esp_aes_release_hardware();
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}
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/*
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* AES-ECB block decryption
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*/
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void esp_aes_decrypt( esp_aes_context *ctx,
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const unsigned char input[16],
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unsigned char output[16] )
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{
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esp_aes_acquire_hardware();
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esp_aes_setkey_hardware(ctx, ESP_AES_DECRYPT);
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esp_aes_block(input, output);
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esp_aes_release_hardware();
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}
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/*
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* AES-ECB block encryption/decryption
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*/
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int esp_aes_crypt_ecb( esp_aes_context *ctx,
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int mode,
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const unsigned char input[16],
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unsigned char output[16] )
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{
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esp_aes_acquire_hardware();
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esp_aes_setkey_hardware(ctx, mode);
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esp_aes_block(input, output);
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esp_aes_release_hardware();
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return 0;
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}
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/*
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* AES-CBC buffer encryption/decryption
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*/
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int esp_aes_crypt_cbc( esp_aes_context *ctx,
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int mode,
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size_t length,
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unsigned char iv[16],
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const unsigned char *input,
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unsigned char *output )
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{
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int i;
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uint32_t *output_words = (uint32_t *)output;
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const uint32_t *input_words = (const uint32_t *)input;
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uint32_t *iv_words = (uint32_t *)iv;
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unsigned char temp[16];
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if ( length % 16 ) {
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return ( ERR_ESP_AES_INVALID_INPUT_LENGTH );
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}
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esp_aes_acquire_hardware();
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esp_aes_setkey_hardware(ctx, mode);
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if ( mode == ESP_AES_DECRYPT ) {
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while ( length > 0 ) {
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memcpy(temp, input_words, 16);
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esp_aes_block(input_words, output_words);
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for ( i = 0; i < 4; i++ ) {
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output_words[i] = output_words[i] ^ iv_words[i];
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}
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memcpy( iv_words, temp, 16 );
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input_words += 4;
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output_words += 4;
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length -= 16;
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}
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} else { // ESP_AES_ENCRYPT
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while ( length > 0 ) {
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for ( i = 0; i < 4; i++ ) {
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output_words[i] = input_words[i] ^ iv_words[i];
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}
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esp_aes_block(output_words, output_words);
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memcpy( iv_words, output_words, 16 );
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input_words += 4;
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output_words += 4;
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length -= 16;
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}
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}
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esp_aes_release_hardware();
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return 0;
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}
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/*
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* AES-CFB128 buffer encryption/decryption
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*/
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int esp_aes_crypt_cfb128( esp_aes_context *ctx,
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int mode,
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size_t length,
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size_t *iv_off,
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unsigned char iv[16],
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const unsigned char *input,
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unsigned char *output )
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{
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int c;
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size_t n = *iv_off;
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esp_aes_acquire_hardware();
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esp_aes_setkey_hardware(ctx, ESP_AES_ENCRYPT);
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if ( mode == ESP_AES_DECRYPT ) {
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while ( length-- ) {
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if ( n == 0 ) {
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esp_aes_block(iv, iv );
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}
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c = *input++;
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*output++ = (unsigned char)( c ^ iv[n] );
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iv[n] = (unsigned char) c;
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n = ( n + 1 ) & 0x0F;
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}
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} else {
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while ( length-- ) {
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if ( n == 0 ) {
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esp_aes_block(iv, iv );
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}
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iv[n] = *output++ = (unsigned char)( iv[n] ^ *input++ );
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n = ( n + 1 ) & 0x0F;
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}
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}
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*iv_off = n;
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esp_aes_release_hardware();
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return 0;
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}
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/*
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* AES-CFB8 buffer encryption/decryption
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*/
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int esp_aes_crypt_cfb8( esp_aes_context *ctx,
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int mode,
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size_t length,
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unsigned char iv[16],
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const unsigned char *input,
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unsigned char *output )
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{
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unsigned char c;
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unsigned char ov[17];
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esp_aes_acquire_hardware();
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esp_aes_setkey_hardware(ctx, ESP_AES_ENCRYPT);
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while ( length-- ) {
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memcpy( ov, iv, 16 );
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esp_aes_block(iv, iv);
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if ( mode == ESP_AES_DECRYPT ) {
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ov[16] = *input;
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}
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c = *output++ = (unsigned char)( iv[0] ^ *input++ );
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if ( mode == ESP_AES_ENCRYPT ) {
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ov[16] = c;
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}
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memcpy( iv, ov + 1, 16 );
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}
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esp_aes_release_hardware();
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return 0;
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}
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/*
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* AES-CTR buffer encryption/decryption
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*/
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int esp_aes_crypt_ctr( esp_aes_context *ctx,
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size_t length,
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size_t *nc_off,
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unsigned char nonce_counter[16],
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unsigned char stream_block[16],
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const unsigned char *input,
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unsigned char *output )
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{
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int c, i;
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size_t n = *nc_off;
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esp_aes_acquire_hardware();
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esp_aes_setkey_hardware(ctx, ESP_AES_ENCRYPT);
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while ( length-- ) {
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if ( n == 0 ) {
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esp_aes_block(nonce_counter, stream_block);
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for ( i = 16; i > 0; i-- )
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if ( ++nonce_counter[i - 1] != 0 ) {
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break;
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}
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}
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c = *input++;
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*output++ = (unsigned char)( c ^ stream_block[n] );
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n = ( n + 1 ) & 0x0F;
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}
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*nc_off = n;
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esp_aes_release_hardware();
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return 0;
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}
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