Angus Gratton 5122154dbb efuse/flash encryption: Reduce FLASH_CRYPT_CNT to a 7 bit efuse field ... 8th bit is not used by hardware. As reported https://esp32.com/viewtopic.php?f=2&t=7800&p=40895#p40894		2019-04-09 09:59:35 +10:00
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esp32	efuse/flash encryption: Reduce FLASH_CRYPT_CNT to a 7 bit efuse field	2019-04-09 09:59:35 +10:00
include/soc	Merge branch 'bugfix/redirect_psram_muxes_to_single_mux' into 'master'	2018-03-14 17:51:50 +08:00
test	soc: add source code of rtc_clk, rtc_pm	2017-04-11 15:45:54 +08:00
component.mk	Add initial SPI RAM support. This adds support for an ESP-PSRAM32 chip connected to the default flash pins and GPIO 16 and 17. The RAM is mapped to address 0x3F800000, but otherwise ignored by esp-idf as of yet.	2017-09-04 12:05:49 +08:00