Omar Chebib a8b1475fe7 feat(riscv): implement coprocessors save area and FPU support ... This commit mainly targets the ESP32-P4. It adds supports for coprocessors on RISC-V based targets. The coprocessor save area, describing the used coprocessors is stored at the end of the stack of each task (highest address) whereas each coprocessor save area is allocated at the beginning of the task (lowest address). The context of each coprocessor is saved lazily, by the task that want to use it.		2023-10-23 11:10:28 +08:00
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debug_stubs.c	esp_system: fix and reenable no-format warning	2023-03-28 13:42:44 +02:00
esp_ipc_isr_handler.S	feat(esp_system): Support IPC_ISR for ESP32P4	2023-09-15 23:38:12 +08:00
esp_ipc_isr_port.c	feat(esp_system): Support IPC_ISR for ESP32P4	2023-09-15 23:38:12 +08:00
esp_ipc_isr_routines.c	feat(esp_system): Support IPC_ISR for ESP32P4	2023-09-15 23:38:12 +08:00
expression_with_stack.c	feat(esp_system): implement hw stack guard for riscv chips	2023-07-01 16:27:40 +00:00
panic_arch.c	feat(riscv): implement coprocessors save area and FPU support	2023-10-23 11:10:28 +08:00