mirror of
https://github.com/espressif/esp-idf.git
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422 lines
13 KiB
C
422 lines
13 KiB
C
/*
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* SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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#include "esp_efuse.h"
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#include <assert.h>
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#include "esp_efuse_table.h"
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// md5_digest_table 6256f9b7c6783e0b651bf52b5b162aa8
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// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
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// If you want to change some fields, you need to change esp_efuse_table.csv file
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// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
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// To show efuse_table run the command 'show_efuse_table'.
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#define MAX_BLK_LEN CONFIG_EFUSE_MAX_BLK_LEN
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// The last free bit in the block is counted over the entire file.
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#define LAST_FREE_BIT_BLK1 MAX_BLK_LEN
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#define LAST_FREE_BIT_BLK2 MAX_BLK_LEN
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#define LAST_FREE_BIT_BLK3 192
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_Static_assert(LAST_FREE_BIT_BLK1 <= MAX_BLK_LEN, "The eFuse table does not match the coding scheme. Edit the table and restart the efuse_common_table or efuse_custom_table command to regenerate the new files.");
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_Static_assert(LAST_FREE_BIT_BLK2 <= MAX_BLK_LEN, "The eFuse table does not match the coding scheme. Edit the table and restart the efuse_common_table or efuse_custom_table command to regenerate the new files.");
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_Static_assert(LAST_FREE_BIT_BLK3 <= MAX_BLK_LEN, "The eFuse table does not match the coding scheme. Edit the table and restart the efuse_common_table or efuse_custom_table command to regenerate the new files.");
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static const esp_efuse_desc_t MAC_FACTORY[] = {
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{EFUSE_BLK0, 72, 8}, // Factory MAC addr [0],
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{EFUSE_BLK0, 64, 8}, // Factory MAC addr [1],
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{EFUSE_BLK0, 56, 8}, // Factory MAC addr [2],
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{EFUSE_BLK0, 48, 8}, // Factory MAC addr [3],
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{EFUSE_BLK0, 40, 8}, // Factory MAC addr [4],
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{EFUSE_BLK0, 32, 8}, // Factory MAC addr [5],
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};
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static const esp_efuse_desc_t MAC_FACTORY_CRC[] = {
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{EFUSE_BLK0, 80, 8}, // CRC8 for factory MAC address,
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};
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static const esp_efuse_desc_t MAC_CUSTOM_CRC[] = {
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{EFUSE_BLK3, 0, 8}, // CRC8 for custom MAC address.,
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};
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static const esp_efuse_desc_t MAC_CUSTOM[] = {
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{EFUSE_BLK3, 8, 48}, // Custom MAC,
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};
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static const esp_efuse_desc_t MAC_CUSTOM_VER[] = {
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{EFUSE_BLK3, 184, 8}, // Custom MAC version,
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};
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static const esp_efuse_desc_t SECURE_BOOT_KEY[] = {
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{EFUSE_BLK2, 0, MAX_BLK_LEN}, // Security boot. Key. (length = "None" - 256. "3/4" - 192. "REPEAT" - 128),
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};
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static const esp_efuse_desc_t ABS_DONE_0[] = {
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{EFUSE_BLK0, 196, 1}, // Secure boot V1 is enabled for bootloader image. EFUSE_RD_ABS_DONE_0,
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};
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static const esp_efuse_desc_t ABS_DONE_1[] = {
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{EFUSE_BLK0, 197, 1}, // Secure boot V2 is enabled for bootloader image. EFUSE_RD_ABS_DONE_1,
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};
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static const esp_efuse_desc_t ENCRYPT_FLASH_KEY[] = {
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{EFUSE_BLK1, 0, MAX_BLK_LEN}, // Flash encrypt. Key. (length = "None" - 256. "3/4" - 192. "REPEAT" - 128),
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};
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static const esp_efuse_desc_t ENCRYPT_CONFIG[] = {
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{EFUSE_BLK0, 188, 4}, // Flash encrypt. EFUSE_FLASH_CRYPT_CONFIG_M,
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};
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static const esp_efuse_desc_t DISABLE_DL_ENCRYPT[] = {
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{EFUSE_BLK0, 199, 1}, // Flash encrypt. Disable UART bootloader encryption. EFUSE_DISABLE_DL_ENCRYPT.,
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};
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static const esp_efuse_desc_t DISABLE_DL_DECRYPT[] = {
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{EFUSE_BLK0, 200, 1}, // Flash encrypt. Disable UART bootloader decryption. EFUSE_DISABLE_DL_DECRYPT.,
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};
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static const esp_efuse_desc_t DISABLE_DL_CACHE[] = {
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{EFUSE_BLK0, 201, 1}, // Flash encrypt. Disable UART bootloader MMU cache. EFUSE_DISABLE_DL_CACHE.,
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};
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static const esp_efuse_desc_t FLASH_CRYPT_CNT[] = {
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{EFUSE_BLK0, 20, 7}, // Flash encrypt. Flash encryption is enabled if this field has an odd number of bits set. EFUSE_FLASH_CRYPT_CNT.,
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};
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static const esp_efuse_desc_t DISABLE_JTAG[] = {
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{EFUSE_BLK0, 198, 1}, // Disable JTAG. EFUSE_RD_DISABLE_JTAG.,
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};
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static const esp_efuse_desc_t CONSOLE_DEBUG_DISABLE[] = {
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{EFUSE_BLK0, 194, 1}, // Disable ROM BASIC interpreter fallback. EFUSE_RD_CONSOLE_DEBUG_DISABLE.,
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};
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static const esp_efuse_desc_t UART_DOWNLOAD_DIS[] = {
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{EFUSE_BLK0, 27, 1}, // Disable UART download mode. Valid for ESP32 V3 and newer,
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};
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static const esp_efuse_desc_t WR_DIS_EFUSE_RD_DISABLE[] = {
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{EFUSE_BLK0, 0, 1}, // Write protection for EFUSE_RD_DISABLE,
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};
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static const esp_efuse_desc_t WR_DIS_FLASH_CRYPT_CNT[] = {
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{EFUSE_BLK0, 2, 1}, // Flash encrypt. Write protection FLASH_CRYPT_CNT,
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};
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static const esp_efuse_desc_t WR_DIS_BLK1[] = {
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{EFUSE_BLK0, 7, 1}, // Flash encrypt. Write protection encryption key. EFUSE_WR_DIS_BLK1,
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};
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static const esp_efuse_desc_t WR_DIS_BLK2[] = {
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{EFUSE_BLK0, 8, 1}, // Security boot. Write protection security key. EFUSE_WR_DIS_BLK2,
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};
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static const esp_efuse_desc_t WR_DIS_BLK3[] = {
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{EFUSE_BLK0, 9, 1}, // Write protection for EFUSE_BLK3. EFUSE_WR_DIS_BLK3,
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};
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static const esp_efuse_desc_t RD_DIS_BLK1[] = {
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{EFUSE_BLK0, 16, 1}, // Flash encrypt. efuse_key_read_protected. EFUSE_RD_DIS_BLK1,
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};
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static const esp_efuse_desc_t RD_DIS_BLK2[] = {
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{EFUSE_BLK0, 17, 1}, // Security boot. efuse_key_read_protected. EFUSE_RD_DIS_BLK2,
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};
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static const esp_efuse_desc_t RD_DIS_BLK3[] = {
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{EFUSE_BLK0, 18, 1}, // Read protection for EFUSE_BLK3. EFUSE_RD_DIS_BLK3,
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};
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static const esp_efuse_desc_t CHIP_VER_DIS_APP_CPU[] = {
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{EFUSE_BLK0, 96, 1}, // EFUSE_RD_CHIP_VER_DIS_APP_CPU,
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};
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static const esp_efuse_desc_t CHIP_VER_DIS_BT[] = {
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{EFUSE_BLK0, 97, 1}, // EFUSE_RD_CHIP_VER_DIS_BT,
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};
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static const esp_efuse_desc_t CHIP_VER_PKG[] = {
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{EFUSE_BLK0, 105, 3}, // EFUSE_RD_CHIP_VER_PKG least significant bits,
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{EFUSE_BLK0, 98, 1}, // EFUSE_RD_CHIP_VER_PKG_4BIT most significant bit,
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};
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static const esp_efuse_desc_t CHIP_CPU_FREQ_LOW[] = {
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{EFUSE_BLK0, 108, 1}, // EFUSE_RD_CHIP_CPU_FREQ_LOW,
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};
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static const esp_efuse_desc_t CHIP_CPU_FREQ_RATED[] = {
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{EFUSE_BLK0, 109, 1}, // EFUSE_RD_CHIP_CPU_FREQ_RATED,
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};
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static const esp_efuse_desc_t CHIP_VER_REV1[] = {
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{EFUSE_BLK0, 111, 1}, // EFUSE_RD_CHIP_VER_REV1,
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};
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static const esp_efuse_desc_t CHIP_VER_REV2[] = {
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{EFUSE_BLK0, 180, 1}, // EFUSE_RD_CHIP_VER_REV2,
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};
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static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = {
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{EFUSE_BLK0, 184, 2}, // WAFER_VERSION_MINOR,
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};
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static const esp_efuse_desc_t XPD_SDIO_REG[] = {
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{EFUSE_BLK0, 142, 1}, // EFUSE_RD_XPD_SDIO_REG,
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};
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static const esp_efuse_desc_t SDIO_TIEH[] = {
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{EFUSE_BLK0, 143, 1}, // EFUSE_RD_SDIO_TIEH,
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};
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static const esp_efuse_desc_t SDIO_FORCE[] = {
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{EFUSE_BLK0, 144, 1}, // EFUSE_RD_SDIO_FORCE,
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};
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static const esp_efuse_desc_t ADC_VREF_AND_SDIO_DREF[] = {
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{EFUSE_BLK0, 136, 6}, // EFUSE_RD_ADC_VREF[0..4] or ( SDIO_DREFH[0 1],
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};
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static const esp_efuse_desc_t ADC1_TP_LOW[] = {
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{EFUSE_BLK3, 96, 7}, // TP_REG EFUSE_RD_ADC1_TP_LOW,
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};
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static const esp_efuse_desc_t ADC2_TP_LOW[] = {
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{EFUSE_BLK3, 112, 7}, // TP_REG EFUSE_RD_ADC2_TP_LOW,
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};
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static const esp_efuse_desc_t ADC1_TP_HIGH[] = {
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{EFUSE_BLK3, 103, 9}, // TP_REG EFUSE_RD_ADC1_TP_HIGH,
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};
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static const esp_efuse_desc_t ADC2_TP_HIGH[] = {
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{EFUSE_BLK3, 119, 9}, // TP_REG EFUSE_RD_ADC2_TP_HIGH,
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};
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static const esp_efuse_desc_t SECURE_VERSION[] = {
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{EFUSE_BLK3, 128, 32}, // Secure version for anti-rollback,
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};
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const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[] = {
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&MAC_FACTORY[0], // Factory MAC addr [0]
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&MAC_FACTORY[1], // Factory MAC addr [1]
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&MAC_FACTORY[2], // Factory MAC addr [2]
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&MAC_FACTORY[3], // Factory MAC addr [3]
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&MAC_FACTORY[4], // Factory MAC addr [4]
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&MAC_FACTORY[5], // Factory MAC addr [5]
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY_CRC[] = {
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&MAC_FACTORY_CRC[0], // CRC8 for factory MAC address
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_MAC_CUSTOM_CRC[] = {
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&MAC_CUSTOM_CRC[0], // CRC8 for custom MAC address.
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_MAC_CUSTOM[] = {
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&MAC_CUSTOM[0], // Custom MAC
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_MAC_CUSTOM_VER[] = {
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&MAC_CUSTOM_VER[0], // Custom MAC version
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY[] = {
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&SECURE_BOOT_KEY[0], // Security boot. Key. (length = "None" - 256. "3/4" - 192. "REPEAT" - 128)
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_ABS_DONE_0[] = {
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&ABS_DONE_0[0], // Secure boot V1 is enabled for bootloader image. EFUSE_RD_ABS_DONE_0
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_ABS_DONE_1[] = {
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&ABS_DONE_1[0], // Secure boot V2 is enabled for bootloader image. EFUSE_RD_ABS_DONE_1
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_ENCRYPT_FLASH_KEY[] = {
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&ENCRYPT_FLASH_KEY[0], // Flash encrypt. Key. (length = "None" - 256. "3/4" - 192. "REPEAT" - 128)
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_ENCRYPT_CONFIG[] = {
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&ENCRYPT_CONFIG[0], // Flash encrypt. EFUSE_FLASH_CRYPT_CONFIG_M
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_DISABLE_DL_ENCRYPT[] = {
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&DISABLE_DL_ENCRYPT[0], // Flash encrypt. Disable UART bootloader encryption. EFUSE_DISABLE_DL_ENCRYPT.
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_DISABLE_DL_DECRYPT[] = {
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&DISABLE_DL_DECRYPT[0], // Flash encrypt. Disable UART bootloader decryption. EFUSE_DISABLE_DL_DECRYPT.
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_DISABLE_DL_CACHE[] = {
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&DISABLE_DL_CACHE[0], // Flash encrypt. Disable UART bootloader MMU cache. EFUSE_DISABLE_DL_CACHE.
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_FLASH_CRYPT_CNT[] = {
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&FLASH_CRYPT_CNT[0], // Flash encrypt. Flash encryption is enabled if this field has an odd number of bits set. EFUSE_FLASH_CRYPT_CNT.
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_DISABLE_JTAG[] = {
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&DISABLE_JTAG[0], // Disable JTAG. EFUSE_RD_DISABLE_JTAG.
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_CONSOLE_DEBUG_DISABLE[] = {
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&CONSOLE_DEBUG_DISABLE[0], // Disable ROM BASIC interpreter fallback. EFUSE_RD_CONSOLE_DEBUG_DISABLE.
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_UART_DOWNLOAD_DIS[] = {
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&UART_DOWNLOAD_DIS[0], // Disable UART download mode. Valid for ESP32 V3 and newer
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_EFUSE_RD_DISABLE[] = {
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&WR_DIS_EFUSE_RD_DISABLE[0], // Write protection for EFUSE_RD_DISABLE
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CRYPT_CNT[] = {
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&WR_DIS_FLASH_CRYPT_CNT[0], // Flash encrypt. Write protection FLASH_CRYPT_CNT
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[] = {
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&WR_DIS_BLK1[0], // Flash encrypt. Write protection encryption key. EFUSE_WR_DIS_BLK1
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK2[] = {
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&WR_DIS_BLK2[0], // Security boot. Write protection security key. EFUSE_WR_DIS_BLK2
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK3[] = {
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&WR_DIS_BLK3[0], // Write protection for EFUSE_BLK3. EFUSE_WR_DIS_BLK3
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLK1[] = {
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&RD_DIS_BLK1[0], // Flash encrypt. efuse_key_read_protected. EFUSE_RD_DIS_BLK1
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLK2[] = {
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&RD_DIS_BLK2[0], // Security boot. efuse_key_read_protected. EFUSE_RD_DIS_BLK2
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLK3[] = {
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&RD_DIS_BLK3[0], // Read protection for EFUSE_BLK3. EFUSE_RD_DIS_BLK3
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_DIS_APP_CPU[] = {
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&CHIP_VER_DIS_APP_CPU[0], // EFUSE_RD_CHIP_VER_DIS_APP_CPU
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_DIS_BT[] = {
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&CHIP_VER_DIS_BT[0], // EFUSE_RD_CHIP_VER_DIS_BT
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_PKG[] = {
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&CHIP_VER_PKG[0], // EFUSE_RD_CHIP_VER_PKG least significant bits
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&CHIP_VER_PKG[1], // EFUSE_RD_CHIP_VER_PKG_4BIT most significant bit
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_CHIP_CPU_FREQ_LOW[] = {
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&CHIP_CPU_FREQ_LOW[0], // EFUSE_RD_CHIP_CPU_FREQ_LOW
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_CHIP_CPU_FREQ_RATED[] = {
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&CHIP_CPU_FREQ_RATED[0], // EFUSE_RD_CHIP_CPU_FREQ_RATED
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_REV1[] = {
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&CHIP_VER_REV1[0], // EFUSE_RD_CHIP_VER_REV1
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_REV2[] = {
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&CHIP_VER_REV2[0], // EFUSE_RD_CHIP_VER_REV2
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = {
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&WAFER_VERSION_MINOR[0], // WAFER_VERSION_MINOR
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_XPD_SDIO_REG[] = {
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&XPD_SDIO_REG[0], // EFUSE_RD_XPD_SDIO_REG
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_SDIO_TIEH[] = {
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&SDIO_TIEH[0], // EFUSE_RD_SDIO_TIEH
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_SDIO_FORCE[] = {
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&SDIO_FORCE[0], // EFUSE_RD_SDIO_FORCE
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_ADC_VREF_AND_SDIO_DREF[] = {
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&ADC_VREF_AND_SDIO_DREF[0], // EFUSE_RD_ADC_VREF[0..4] or ( SDIO_DREFH[0 1]
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_ADC1_TP_LOW[] = {
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&ADC1_TP_LOW[0], // TP_REG EFUSE_RD_ADC1_TP_LOW
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_ADC2_TP_LOW[] = {
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&ADC2_TP_LOW[0], // TP_REG EFUSE_RD_ADC2_TP_LOW
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_ADC1_TP_HIGH[] = {
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&ADC1_TP_HIGH[0], // TP_REG EFUSE_RD_ADC1_TP_HIGH
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NULL
|
|
};
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|
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const esp_efuse_desc_t* ESP_EFUSE_ADC2_TP_HIGH[] = {
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&ADC2_TP_HIGH[0], // TP_REG EFUSE_RD_ADC2_TP_HIGH
|
|
NULL
|
|
};
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|
|
|
const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = {
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&SECURE_VERSION[0], // Secure version for anti-rollback
|
|
NULL
|
|
};
|