mirror of
https://github.com/espressif/esp-idf.git
synced 2024-09-20 00:36:01 -04:00
631e15c6eb
If LDO1 is used by spi flash, then we recommend to give the ownership to the hardware. Software just read the parameters from the efuse and set to PMU.
465 lines
16 KiB
C
465 lines
16 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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#include "esp_flash.h"
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#include "memspi_host_driver.h"
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#include "esp_flash_spi_init.h"
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#include "driver/gpio.h"
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#include "esp_rom_gpio.h"
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#include "esp_rom_efuse.h"
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#include "esp_log.h"
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#include "esp_heap_caps.h"
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#include "hal/spi_types.h"
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#include "esp_private/spi_share_hw_ctrl.h"
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#include "esp_ldo_regulator.h"
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#include "hal/spi_flash_hal.h"
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#include "hal/gpio_hal.h"
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#include "esp_flash_internal.h"
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#include "esp_rom_gpio.h"
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#include "esp_private/spi_flash_os.h"
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#include "esp_private/cache_utils.h"
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#include "esp_spi_flash_counters.h"
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#include "esp_rom_spiflash.h"
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#include "bootloader_flash.h"
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#include "esp_check.h"
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__attribute__((unused)) static const char TAG[] = "spi_flash";
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/* This pointer is defined in ROM and extern-ed on targets where CONFIG_SPI_FLASH_ROM_IMPL = y*/
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#if !CONFIG_SPI_FLASH_ROM_IMPL
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esp_flash_t *esp_flash_default_chip = NULL;
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#endif
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#if defined CONFIG_ESPTOOLPY_FLASHFREQ_120M
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#define DEFAULT_FLASH_SPEED 120
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#elif defined CONFIG_ESPTOOLPY_FLASHFREQ_80M
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#define DEFAULT_FLASH_SPEED 80
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#elif defined CONFIG_ESPTOOLPY_FLASHFREQ_64M
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#define DEFAULT_FLASH_SPEED 64
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#elif defined CONFIG_ESPTOOLPY_FLASHFREQ_60M
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#define DEFAULT_FLASH_SPEED 60
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#elif defined CONFIG_ESPTOOLPY_FLASHFREQ_48M
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#define DEFAULT_FLASH_SPEED 48
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#elif defined CONFIG_ESPTOOLPY_FLASHFREQ_40M
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#define DEFAULT_FLASH_SPEED 40
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#elif defined CONFIG_ESPTOOLPY_FLASHFREQ_32M
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#define DEFAULT_FLASH_SPEED 32
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#elif defined CONFIG_ESPTOOLPY_FLASHFREQ_30M
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#define DEFAULT_FLASH_SPEED 30
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#elif defined CONFIG_ESPTOOLPY_FLASHFREQ_26M
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#define DEFAULT_FLASH_SPEED 26
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#elif defined CONFIG_ESPTOOLPY_FLASHFREQ_24M
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#define DEFAULT_FLASH_SPEED 24
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#elif defined CONFIG_ESPTOOLPY_FLASHFREQ_20M
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#define DEFAULT_FLASH_SPEED 20
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#elif defined CONFIG_ESPTOOLPY_FLASHFREQ_16M
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#define DEFAULT_FLASH_SPEED 16
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#elif defined CONFIG_ESPTOOLPY_FLASHFREQ_15M
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#define DEFAULT_FLASH_SPEED 15
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#elif defined CONFIG_ESPTOOLPY_FLASHFREQ_12M
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#define DEFAULT_FLASH_SPEED 12
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#else
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#error Flash frequency not defined! Check the ``CONFIG_ESPTOOLPY_FLASHFREQ_*`` options.
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#endif
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#if defined(CONFIG_ESPTOOLPY_FLASHMODE_QIO)
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#define DEFAULT_FLASH_MODE SPI_FLASH_QIO
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#define FLASH_MODE_STRING "qio"
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#elif defined(CONFIG_ESPTOOLPY_FLASHMODE_QOUT)
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#define DEFAULT_FLASH_MODE SPI_FLASH_QOUT
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#define FLASH_MODE_STRING "qout"
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#elif defined(CONFIG_ESPTOOLPY_FLASHMODE_DIO)
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#define DEFAULT_FLASH_MODE SPI_FLASH_DIO
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#define FLASH_MODE_STRING "dio"
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#elif defined(CONFIG_ESPTOOLPY_FLASHMODE_DOUT)
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#define DEFAULT_FLASH_MODE SPI_FLASH_DOUT
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#define FLASH_MODE_STRING "dout"
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#elif defined(CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR)
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#define DEFAULT_FLASH_MODE SPI_FLASH_OPI_STR
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#define FLASH_MODE_STRING "opi_str"
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#elif defined(CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_DTR)
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#define DEFAULT_FLASH_MODE SPI_FLASH_OPI_DTR
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#define FLASH_MODE_STRING "opi_dtr"
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#else
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#define DEFAULT_FLASH_MODE SPI_FLASH_FASTRD
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#define FLASH_MODE_STRING "fast_rd"
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#endif
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//TODO: modify cs hold to meet requirements of all chips!!!
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#if CONFIG_IDF_TARGET_ESP32
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#define ESP_FLASH_HOST_CONFIG_DEFAULT() (memspi_host_config_t){ \
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.host_id = SPI1_HOST,\
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.freq_mhz = DEFAULT_FLASH_SPEED, \
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.cs_num = 0, \
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.iomux = false, \
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.input_delay_ns = 0,\
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.cs_setup = 1,\
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}
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#else // Other target
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#if !CONFIG_SPI_FLASH_AUTO_SUSPEND
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#define ESP_FLASH_HOST_CONFIG_DEFAULT() (memspi_host_config_t){ \
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.host_id = SPI1_HOST,\
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.freq_mhz = DEFAULT_FLASH_SPEED, \
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.cs_num = 0, \
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.iomux = true, \
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.input_delay_ns = 0,\
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.cs_setup = 1,\
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}
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#else
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#define ESP_FLASH_HOST_CONFIG_DEFAULT() (memspi_host_config_t){ \
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.host_id = SPI1_HOST,\
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.freq_mhz = DEFAULT_FLASH_SPEED, \
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.cs_num = 0, \
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.iomux = true, \
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.input_delay_ns = 0,\
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.auto_sus_en = true,\
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.cs_setup = 1,\
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}
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#define TSUS_VAL_SUSPEND CONFIG_SPI_FLASH_SUSPEND_TSUS_VAL_US
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#endif //!CONFIG_SPI_FLASH_AUTO_SUSPEND
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#endif // Other target
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static IRAM_ATTR NOINLINE_ATTR void cs_initialize(esp_flash_t *chip, const esp_flash_spi_device_config_t *config, bool cs_use_iomux, int cs_id)
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{
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//Not using spicommon_cs_initialize since we don't want to put the whole
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//spi_periph_signal into the DRAM. Copy these data from flash before the
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//cache disabling
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int cs_io_num = config->cs_io_num;
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int spics_in = spi_periph_signal[config->host_id].spics_in;
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int spics_out = spi_periph_signal[config->host_id].spics_out[cs_id];
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int spics_func = spi_periph_signal[config->host_id].func;
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gpio_hal_context_t gpio_hal = {
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.dev = GPIO_HAL_GET_HW(GPIO_PORT_0)
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};
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//To avoid the panic caused by flash data line conflicts during cs line
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//initialization, disable the cache temporarily
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chip->os_func->start(chip->os_func_data);
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gpio_hal_input_enable(&gpio_hal, cs_io_num);
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if (cs_use_iomux) {
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gpio_hal_func_sel(&gpio_hal, cs_io_num, spics_func);
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} else {
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gpio_hal_output_enable(&gpio_hal, cs_io_num);
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gpio_hal_od_disable(&gpio_hal, cs_io_num);
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esp_rom_gpio_connect_out_signal(cs_io_num, spics_out, false, false);
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if (cs_id == 0) {
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esp_rom_gpio_connect_in_signal(cs_io_num, spics_in, false);
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}
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gpio_hal_func_sel(&gpio_hal, cs_io_num, PIN_FUNC_GPIO);
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}
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chip->os_func->end(chip->os_func_data);
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}
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static bool use_bus_lock(int host_id)
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{
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if (host_id != SPI1_HOST) {
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return true;
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}
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#if CONFIG_SPI_FLASH_SHARE_SPI1_BUS
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return true;
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#else
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return false;
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#endif
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}
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static bool bus_using_iomux(spi_host_device_t host)
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{
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CHECK_IOMUX_PIN(host, spid);
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CHECK_IOMUX_PIN(host, spiq);
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CHECK_IOMUX_PIN(host, spiwp);
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CHECK_IOMUX_PIN(host, spihd);
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return true;
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}
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static bool cs_using_iomux(const esp_flash_spi_device_config_t *config)
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{
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bool use_iomux = true;
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CHECK_IOMUX_PIN(config->host_id, spics);
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if (config->cs_io_num != spi_periph_signal[config->host_id].spics_in) {
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use_iomux = false;
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}
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return use_iomux;
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}
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static esp_err_t acquire_spi_device(const esp_flash_spi_device_config_t *config, int* out_dev_id, spi_bus_lock_dev_handle_t* out_dev_handle)
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{
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esp_err_t ret = ESP_OK;
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int dev_id = -1;
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spi_bus_lock_dev_handle_t dev_handle = NULL;
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if (use_bus_lock(config->host_id)) {
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spi_bus_lock_handle_t lock = spi_bus_lock_get_by_id(config->host_id);
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spi_bus_lock_dev_config_t config = {.flags = SPI_BUS_LOCK_DEV_FLAG_CS_REQUIRED};
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ret = spi_bus_lock_register_dev(lock, &config, &dev_handle);
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if (ret == ESP_OK) {
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dev_id = spi_bus_lock_get_dev_id(dev_handle);
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} else if (ret == ESP_ERR_NOT_SUPPORTED) {
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ESP_LOGE(TAG, "No free CS.");
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} else if (ret == ESP_ERR_INVALID_ARG) {
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ESP_LOGE(TAG, "Bus lock not initialized (check CONFIG_SPI_FLASH_SHARE_SPI1_BUS).");
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}
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} else {
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const bool is_main_flash = (config->host_id == SPI1_HOST && config->cs_id == 0);
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if (config->cs_id >= SOC_SPI_PERIPH_CS_NUM(config->host_id) || config->cs_id < 0 || is_main_flash) {
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ESP_LOGE(TAG, "Not valid CS.");
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ret = ESP_ERR_INVALID_ARG;
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} else {
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dev_id = config->cs_id;
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assert(dev_handle == NULL);
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}
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}
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*out_dev_handle = dev_handle;
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*out_dev_id = dev_id;
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return ret;
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}
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esp_err_t spi_bus_add_flash_device(esp_flash_t **out_chip, const esp_flash_spi_device_config_t *config)
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{
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if (out_chip == NULL) {
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return ESP_ERR_INVALID_ARG;
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}
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if (!GPIO_IS_VALID_OUTPUT_GPIO(config->cs_io_num)) {
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return ESP_ERR_INVALID_ARG;
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}
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esp_flash_t *chip = NULL;
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memspi_host_inst_t *host = NULL;
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esp_err_t ret = ESP_OK;
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uint32_t caps = MALLOC_CAP_DEFAULT;
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if (config->host_id == SPI1_HOST) caps = MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT;
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chip = (esp_flash_t*)heap_caps_malloc(sizeof(esp_flash_t), caps);
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if (!chip) {
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ret = ESP_ERR_NO_MEM;
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goto fail;
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}
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host = (memspi_host_inst_t*)heap_caps_malloc(sizeof(memspi_host_inst_t), caps);
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*chip = (esp_flash_t) {
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.read_mode = config->io_mode,
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.host = (spi_flash_host_inst_t*)host,
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};
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if (!host) {
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ret = ESP_ERR_NO_MEM;
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goto fail;
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}
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int dev_id;
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spi_bus_lock_dev_handle_t dev_handle;
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esp_err_t err = acquire_spi_device(config, &dev_id, &dev_handle);
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if (err != ESP_OK) {
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ret = err;
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goto fail;
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}
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err = esp_flash_init_os_functions(chip, config->host_id, dev_handle);
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if (err != ESP_OK) {
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ret = err;
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goto fail;
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}
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//avoid conflicts with main flash
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assert(config->host_id != SPI1_HOST || dev_id != 0);
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bool use_iomux = bus_using_iomux(config->host_id);
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memspi_host_config_t host_cfg = {
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.host_id = config->host_id,
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.cs_num = dev_id,
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.iomux = use_iomux,
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.input_delay_ns = config->input_delay_ns,
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.freq_mhz = config->freq_mhz,
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};
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host_cfg.clock_src_freq = spi_flash_ll_get_source_clock_freq_mhz(host_cfg.host_id);
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err = memspi_host_init_pointers(host, &host_cfg);
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if (err != ESP_OK) {
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ret = err;
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goto fail;
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}
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// The cs_id inside `config` is deprecated, use the `dev_id` provided by the bus lock instead.
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cs_initialize(chip, config, cs_using_iomux(config), dev_id);
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*out_chip = chip;
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return ret;
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fail:
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// The memory allocated are free'd in the `spi_bus_remove_flash_device`.
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spi_bus_remove_flash_device(chip);
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return ret;
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}
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esp_err_t spi_bus_remove_flash_device(esp_flash_t *chip)
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{
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if (chip == NULL) {
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return ESP_ERR_INVALID_ARG;
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}
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spi_bus_lock_dev_handle_t dev_handle = NULL;
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esp_flash_deinit_os_functions(chip, &dev_handle);
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if (dev_handle) {
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spi_bus_lock_unregister_dev(dev_handle);
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}
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free(chip->host);
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free(chip);
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return ESP_OK;
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}
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/* The default (ie initial boot) no-OS ROM esp_flash_os_functions_t */
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extern const esp_flash_os_functions_t esp_flash_noos_functions;
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static DRAM_ATTR memspi_host_inst_t esp_flash_default_host;
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static DRAM_ATTR esp_flash_t default_chip = {
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.read_mode = DEFAULT_FLASH_MODE,
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.host = (spi_flash_host_inst_t*)&esp_flash_default_host,
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.os_func = &esp_flash_noos_functions,
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};
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#if CONFIG_ESPTOOLPY_FLASH_MODE_AUTO_DETECT
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/* This function is used to correct flash mode if config option is not consistent with efuse information */
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static void s_esp_flash_choose_correct_mode(memspi_host_config_t *cfg)
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{
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static const char *mode = FLASH_MODE_STRING;
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if (bootloader_flash_is_octal_mode_enabled()) {
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#if !CONFIG_ESPTOOLPY_FLASHMODE_OPI
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ESP_EARLY_LOGW(TAG, "Octal flash chip is using but %s mode is selected, will automatically switch to Octal mode", mode);
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cfg->octal_mode_en = 1;
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cfg->default_io_mode = SPI_FLASH_OPI_STR;
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default_chip.read_mode = SPI_FLASH_OPI_STR;
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#endif
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} else {
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#if CONFIG_ESPTOOLPY_FLASHMODE_OPI
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ESP_EARLY_LOGW(TAG, "Quad flash chip is using but %s flash mode is selected, will automatically switch to DIO mode", mode);
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cfg->octal_mode_en = 0;
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cfg->default_io_mode = SPI_FLASH_DIO;
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default_chip.read_mode = SPI_FLASH_DIO;
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#endif
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}
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}
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#endif // CONFIG_ESPTOOLPY_FLASH_MODE_AUTO_DETECT
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extern esp_err_t esp_flash_suspend_cmd_init(esp_flash_t* chip);
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esp_err_t esp_flash_init_default_chip(void)
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{
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const esp_rom_spiflash_chip_t *legacy_chip = &g_rom_flashchip;
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memspi_host_config_t cfg = ESP_FLASH_HOST_CONFIG_DEFAULT();
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#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
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// Only these chips have efuses for spi pin configuration.
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cfg.iomux = esp_rom_efuse_get_flash_gpio_info() == 0 ? true : false;
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#endif
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#if CONFIG_ESPTOOLPY_OCT_FLASH
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// Default value. When `CONFIG_ESPTOOLPY_FLASH_MODE_AUTO_DETECT` selected, if the selected mode not consistent with
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// hardware, will be overwritten in s_esp_flash_choose_correct_mode.
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cfg.octal_mode_en = 1;
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cfg.default_io_mode = DEFAULT_FLASH_MODE;
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#endif
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#if CONFIG_ESPTOOLPY_FLASH_MODE_AUTO_DETECT
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// Automatically detect flash mode in run time
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s_esp_flash_choose_correct_mode(&cfg);
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#endif
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// For chips need time tuning, get value directly from system here.
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#if SOC_SPI_MEM_SUPPORT_TIMING_TUNING
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if (spi_flash_timing_is_tuned()) {
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cfg.using_timing_tuning = 1;
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spi_timing_get_flash_timing_param(&cfg.timing_reg);
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}
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#endif // SOC_SPI_MEM_SUPPORT_TIMING_TUNING
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cfg.clock_src_freq = spi_flash_ll_get_source_clock_freq_mhz(cfg.host_id);
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#if CONFIG_SPI_FLASH_AUTO_SUSPEND
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if (TSUS_VAL_SUSPEND > 400 || TSUS_VAL_SUSPEND < 20) {
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// Assume that the tsus value cannot larger than 400 (because the performance might be really bad)
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// And value cannot smaller than 20 (never see that small tsus value, might be wrong)
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return ESP_ERR_INVALID_ARG;
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}
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cfg.tsus_val = TSUS_VAL_SUSPEND;
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#endif // CONFIG_SPI_FLASH_AUTO_SUSPEND
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//the host is already initialized, only do init for the data and load it to the host
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esp_err_t err = memspi_host_init_pointers(&esp_flash_default_host, &cfg);
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if (err != ESP_OK) {
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return err;
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}
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// ROM TODO: account for non-standard default pins in efuse
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// ROM TODO: to account for chips which are slow to power on, maybe keep probing in a loop here
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err = esp_flash_init_main(&default_chip);
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if (err != ESP_OK) {
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return err;
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}
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if (default_chip.size < legacy_chip->chip_size) {
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ESP_EARLY_LOGE(TAG, "Detected size(%dk) smaller than the size in the binary image header(%dk). Probe failed.", default_chip.size/1024, legacy_chip->chip_size/1024);
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return ESP_ERR_FLASH_SIZE_NOT_MATCH;
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}
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if (default_chip.size > legacy_chip->chip_size) {
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ESP_EARLY_LOGW(TAG, "Detected size(%dk) larger than the size in the binary image header(%dk). Using the size in the binary image header.", default_chip.size/1024, legacy_chip->chip_size/1024);
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}
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#if !CONFIG_IDF_TARGET_ESP32P4 || !CONFIG_APP_BUILD_TYPE_RAM // IDF-10019
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if (legacy_chip->chip_size > 16 * 1024 * 1024) {
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ESP_RETURN_ON_ERROR_ISR(esp_mspi_32bit_address_flash_feature_check(), TAG, "32bit address feature check failed");
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}
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#endif // !CONFIG_IDF_TARGET_ESP32P4 || !CONFIG_APP_BUILD_TYPE_RAM
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// Set chip->size equal to ROM flash size(also equal to the size in binary image header), which means the available size that can be used
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default_chip.size = legacy_chip->chip_size;
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esp_flash_default_chip = &default_chip;
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|
#ifdef CONFIG_SPI_FLASH_AUTO_SUSPEND
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err = esp_flash_suspend_cmd_init(&default_chip);
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|
if (err != ESP_OK) {
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|
return err;
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|
}
|
|
#endif
|
|
|
|
#if CONFIG_SPI_FLASH_HPM_DC_ON
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|
if (spi_flash_hpm_dummy_adjust()) {
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|
default_chip.hpm_dummy_ena = 1;
|
|
}
|
|
#endif
|
|
|
|
return ESP_OK;
|
|
}
|
|
|
|
esp_err_t esp_flash_app_init(void)
|
|
{
|
|
esp_err_t err = ESP_OK;
|
|
|
|
// Acquire the LDO channel used by the SPI NOR flash
|
|
// in case the LDO voltage is changed by other users
|
|
#if CONFIG_ESP_LDO_RESERVE_SPI_NOR_FLASH
|
|
static esp_ldo_channel_handle_t s_ldo_chan = NULL;
|
|
esp_ldo_channel_config_t ldo_config = {
|
|
.chan_id = CONFIG_ESP_LDO_CHAN_SPI_NOR_FLASH_DOMAIN,
|
|
.voltage_mv = CONFIG_ESP_LDO_VOLTAGE_SPI_NOR_FLASH_DOMAIN,
|
|
.flags = {
|
|
.owned_by_hw = true, // LDO output is totally controlled by hardware
|
|
},
|
|
};
|
|
err = esp_ldo_acquire_channel(&ldo_config, &s_ldo_chan);
|
|
if (err != ESP_OK) return err;
|
|
#endif // CONFIG_ESP_LDO_RESERVE_SPI_NOR_FLASH
|
|
|
|
spi_flash_init_lock();
|
|
spi_flash_guard_set(&g_flash_guard_default_ops);
|
|
#if CONFIG_SPI_FLASH_ENABLE_COUNTERS
|
|
esp_flash_reset_counters();
|
|
#endif
|
|
#if CONFIG_SPI_FLASH_SHARE_SPI1_BUS
|
|
err = esp_flash_init_main_bus_lock();
|
|
if (err != ESP_OK) return err;
|
|
#endif
|
|
err = esp_flash_app_enable_os_functions(&default_chip);
|
|
return err;
|
|
}
|