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https://github.com/espressif/esp-idf.git
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117 lines
4.0 KiB
C
117 lines
4.0 KiB
C
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "esp_log.h"
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#include "esp_eth.h"
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#include "eth_phy/phy_reg.h"
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#include "eth_phy/phy_ip101.h"
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#define IP101_PHY_ID1 0x243
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#define IP101_PHY_ID2 0xc54
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#define IP101_PHY_ID2_MASK 0xFFF0
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#define PHY_STATUS_REG (0x1e)
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#define DUPLEX_STATUS BIT(2)
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#define SPEED_STATUS BIT(1)
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static const char *TAG = "ip101";
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void phy_ip101_check_phy_init(void)
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{
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phy_ip101_dump_registers();
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esp_eth_smi_wait_set(MII_BASIC_MODE_STATUS_REG, MII_AUTO_NEGOTIATION_COMPLETE, 0);
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}
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eth_speed_mode_t phy_ip101_get_speed_mode(void)
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{
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if ((esp_eth_smi_read(PHY_STATUS_REG) & SPEED_STATUS) == SPEED_STATUS) {
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ESP_LOGD(TAG, "phy_ip101_get_speed_mode(100)");
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return ETH_SPEED_MODE_100M;
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} else {
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ESP_LOGD(TAG, "phy_ip101_get_speed_mode(10)");
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return ETH_SPEED_MODE_10M;
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}
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}
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eth_duplex_mode_t phy_ip101_get_duplex_mode(void)
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{
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if ((esp_eth_smi_read(PHY_STATUS_REG) & DUPLEX_STATUS) == DUPLEX_STATUS) {
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ESP_LOGD(TAG, "phy_ip101_get_duplex_mode(FULL)");
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return ETH_MODE_FULLDUPLEX;
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} else {
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ESP_LOGD(TAG, "phy_ip101_get_duplex_mode(HALF)");
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return ETH_MODE_HALFDUPLEX;
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}
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}
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void phy_ip101_power_enable(bool enable)
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{
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if (enable) {
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uint32_t data = esp_eth_smi_read(MII_BASIC_MODE_CONTROL_REG);
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data |= MII_AUTO_NEGOTIATION_ENABLE | MII_RESTART_AUTO_NEGOTIATION;
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esp_eth_smi_write(MII_BASIC_MODE_CONTROL_REG, data);
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// TODO: only do this if config.flow_ctrl_enable == true
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phy_mii_enable_flow_ctrl();
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}
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}
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esp_err_t phy_ip101_init(void)
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{
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esp_err_t res1, res2;
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ESP_LOGD(TAG, "phy_ip101_init()");
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phy_ip101_dump_registers();
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do {
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// Call esp_eth_smi_wait_value() with a timeout so it prints an error periodically
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res1 = esp_eth_smi_wait_value(MII_PHY_IDENTIFIER_1_REG, IP101_PHY_ID1, UINT16_MAX, 1000);
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res2 = esp_eth_smi_wait_value(MII_PHY_IDENTIFIER_2_REG, IP101_PHY_ID2, IP101_PHY_ID2_MASK, 1000);
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} while (res1 != ESP_OK || res2 != ESP_OK);
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ets_delay_us(300);
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// TODO: only do this if config.flow_ctrl_enable == true
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phy_mii_enable_flow_ctrl();
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if (res1 == ESP_OK && res2 == ESP_OK) {
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return ESP_OK;
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} else {
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return ESP_ERR_TIMEOUT;
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}
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}
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const eth_config_t phy_ip101_default_ethernet_config = {
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.phy_addr = 0x1,
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.mac_mode = ETH_MODE_RMII,
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.clock_mode = ETH_CLOCK_GPIO0_OUT,
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.flow_ctrl_enable = true,
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.phy_init = phy_ip101_init,
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.phy_check_init = phy_ip101_check_phy_init,
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.phy_check_link = phy_mii_check_link_status,
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.phy_get_speed_mode = phy_ip101_get_speed_mode,
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.phy_get_duplex_mode = phy_ip101_get_duplex_mode,
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.phy_get_partner_pause_enable = phy_mii_get_partner_pause_enable,
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.phy_power_enable = phy_ip101_power_enable,
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};
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void phy_ip101_dump_registers()
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{
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ESP_LOGD(TAG, "IP101 Registers:");
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ESP_LOGD(TAG, "BCR 0x%04x", esp_eth_smi_read(0x0));
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ESP_LOGD(TAG, "BSR 0x%04x", esp_eth_smi_read(0x1));
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ESP_LOGD(TAG, "PHY1 0x%04x", esp_eth_smi_read(0x2));
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ESP_LOGD(TAG, "PHY2 0x%04x", esp_eth_smi_read(0x3));
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ESP_LOGD(TAG, "ANAR 0x%04x", esp_eth_smi_read(0x4));
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ESP_LOGD(TAG, "ANLPAR 0x%04x", esp_eth_smi_read(0x5));
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ESP_LOGD(TAG, "ANER 0x%04x", esp_eth_smi_read(0x6));
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ESP_LOGD(TAG, "PSCR 0x%04x", esp_eth_smi_read(0x16));
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ESP_LOGD(TAG, "ISR 0x%04x", esp_eth_smi_read(0x17));
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ESP_LOGD(TAG, "ICR 0x%04x", esp_eth_smi_read(0x18));
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ESP_LOGD(TAG, "CSSR 0x%04x", esp_eth_smi_read(0x30));
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}
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