mirror of
https://github.com/espressif/esp-idf.git
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82 lines
1.9 KiB
Plaintext
82 lines
1.9 KiB
Plaintext
/*
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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#include "soc/soc.h"
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#include "ld.common"
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#if CONFIG_ESP_ROM_HAS_LP_ROM
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/* With LP-ROM memory layout is different due to LP ROM stack/data */
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#define ULP_MEM_START_ADDRESS SOC_RTC_DRAM_LOW + RESERVE_RTC_MEM
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#else
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#define ULP_MEM_START_ADDRESS (SOC_RTC_DRAM_LOW)
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#endif
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#define ALIGN_DOWN(SIZE, AL) (SIZE & ~(AL - 1))
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/* Ensure the end where the shared memory starts is aligned to 8 bytes
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if updating this also update the same in ulp_lp_core_memory_shared.c
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*/
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#define ALIGNED_COPROC_MEM ALIGN_DOWN(CONFIG_ULP_COPROC_RESERVE_MEM, 0x8)
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ENTRY(reset_vector)
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MEMORY
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{
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/*first 128byte for exception/interrupt vectors*/
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vector_table(RX) : ORIGIN = ULP_MEM_START_ADDRESS , LENGTH = 0x80
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ram(RWX) : ORIGIN = ULP_MEM_START_ADDRESS + 0x80, LENGTH = ALIGNED_COPROC_MEM - 0x80 - CONFIG_ULP_SHARED_MEM
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shared_mem_ram(RW) : ORIGIN = ULP_MEM_START_ADDRESS + ALIGNED_COPROC_MEM - CONFIG_ULP_SHARED_MEM, LENGTH = CONFIG_ULP_SHARED_MEM
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}
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SECTIONS
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{
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.vector.text :
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{
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/*exception/interrupt vectors*/
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__mtvec_base = .;
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KEEP (*(.init.vector .init.vector.*))
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} > vector_table
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. = ORIGIN(ram);
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.text ALIGN(4):
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{
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*(.text.vectors) /* Default reset vector must link to offset 0x80 */
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*(.text)
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*(.text*)
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} >ram
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.rodata ALIGN(4):
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{
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*(.rodata)
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*(.rodata*)
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} > ram
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.data ALIGN(4):
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{
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*(.data)
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*(.data*)
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*(.sdata)
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*(.sdata*)
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} > ram
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.bss ALIGN(4) :
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{
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*(.bss)
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*(.bss*)
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*(.sbss)
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*(.sbss*)
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PROVIDE(end = .);
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} >ram
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__stack_top = ORIGIN(ram) + LENGTH(ram);
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. = ORIGIN(shared_mem_ram);
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.shared_mem (ALIGN(4)) :
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{
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KEEP(*(.shared_mem))
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} > shared_mem_ram
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}
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