mirror of
https://github.com/espressif/esp-idf.git
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245 lines
8.1 KiB
C
245 lines
8.1 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include <stdbool.h>
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#include <stdio.h>
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#include "sdkconfig.h"
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#include "hal/wdt_hal.h"
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#include "hal/mwdt_ll.h"
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#include "hal/timer_ll.h"
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#include "esp_check.h"
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#include "esp_err.h"
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#include "esp_attr.h"
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#include "esp_intr_alloc.h"
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#include "esp_log.h"
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#include "esp_private/system_internal.h"
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#include "esp_private/periph_ctrl.h"
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#include "esp_private/esp_task_wdt_impl.h"
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#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_TIMER_SUPPORT_SLEEP_RETENTION
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#include "esp_private/sleep_retention.h"
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#endif
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#define TWDT_INSTANCE WDT_MWDT0
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#define TWDT_TICKS_PER_US 500
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#define TWDT_PRESCALER MWDT_LL_DEFAULT_CLK_PRESCALER // Tick period of 500us if WDT source clock is 80MHz
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#define TWDT_PERIPH_MODULE PERIPH_TIMG0_MODULE
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#define TWDT_TIMER_GROUP 0
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#define TWDT_INTR_SOURCE ETS_TG0_WDT_LEVEL_INTR_SOURCE
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/**
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* Context for the software implementation of the Task WatchDog Timer.
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* This will be passed as a parameter to public functions below. */
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typedef struct {
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wdt_hal_context_t hal;
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intr_handle_t intr_handle;
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} twdt_ctx_hard_t;
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/**
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* Declare the initial context as static. It will be passed to the
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* task_wdt implementation as the implementation context in the
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* init function. */
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static twdt_ctx_hard_t init_context;
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#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_TIMER_SUPPORT_SLEEP_RETENTION
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static const char* TAG = "task_wdt";
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static esp_err_t sleep_task_wdt_retention_init(void *arg)
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{
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uint32_t group_id = *(uint32_t *)arg;
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esp_err_t err = sleep_retention_entries_create(tg_wdt_regs_retention[group_id].link_list,
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tg_wdt_regs_retention[group_id].link_num,
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REGDMA_LINK_PRI_6,
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(group_id == 0) ? SLEEP_RETENTION_MODULE_TG0_WDT : SLEEP_RETENTION_MODULE_TG1_WDT);
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if (err == ESP_OK) {
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ESP_LOGD(TAG, "Task watchdog timer retention initialization");
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}
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ESP_RETURN_ON_ERROR(err, TAG, "Failed to create sleep retention linked list for task watchdog timer");
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return err;
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}
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static esp_err_t esp_task_wdt_retention_enable(uint32_t group_id)
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{
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sleep_retention_module_init_param_t init_param = {
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.cbs = { .create = { .handle = sleep_task_wdt_retention_init, .arg = &group_id } },
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.depends = BIT(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM)
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};
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esp_err_t err = sleep_retention_module_init((group_id == 0) ? SLEEP_RETENTION_MODULE_TG0_WDT : SLEEP_RETENTION_MODULE_TG1_WDT, &init_param);
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if (err == ESP_OK) {
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err = sleep_retention_module_allocate((group_id == 0) ? SLEEP_RETENTION_MODULE_TG0_WDT : SLEEP_RETENTION_MODULE_TG1_WDT);
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if (err != ESP_OK) {
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ESP_LOGW(TAG, "Failed to allocate sleep retention linked list for task watchdog timer retention");
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}
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}
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return err;
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}
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static esp_err_t esp_task_wdt_retention_disable(uint32_t group_id)
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{
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esp_err_t err = sleep_retention_module_free((group_id == 0) ? SLEEP_RETENTION_MODULE_TG0_WDT : SLEEP_RETENTION_MODULE_TG1_WDT);
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if (err == ESP_OK) {
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err = sleep_retention_module_deinit((group_id == 0) ? SLEEP_RETENTION_MODULE_TG0_WDT : SLEEP_RETENTION_MODULE_TG1_WDT);
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}
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return err;
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}
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#endif
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esp_err_t esp_task_wdt_impl_timer_allocate(const esp_task_wdt_config_t *config,
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twdt_isr_callback callback,
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twdt_ctx_t *obj)
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{
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esp_err_t ret = ESP_OK;
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twdt_ctx_hard_t *ctx = &init_context;
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if (config == NULL || obj == NULL) {
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ret = ESP_ERR_INVALID_STATE;
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}
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if (ret == ESP_OK) {
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esp_intr_alloc(TWDT_INTR_SOURCE, 0, callback, NULL, &ctx->intr_handle);
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}
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if (ret == ESP_OK) {
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// enable bus clock for the timer group registers
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PERIPH_RCC_ACQUIRE_ATOMIC(TWDT_PERIPH_MODULE, ref_count) {
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if (ref_count == 0) {
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timer_ll_enable_bus_clock(TWDT_TIMER_GROUP, true);
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timer_ll_reset_register(TWDT_TIMER_GROUP);
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}
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}
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wdt_hal_init(&ctx->hal, TWDT_INSTANCE, TWDT_PRESCALER, true);
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wdt_hal_write_protect_disable(&ctx->hal);
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// Configure 1st stage timeout and behavior
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wdt_hal_config_stage(&ctx->hal, WDT_STAGE0, config->timeout_ms * (1000 / TWDT_TICKS_PER_US), WDT_STAGE_ACTION_INT);
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// Configure 2nd stage timeout and behavior
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wdt_hal_config_stage(&ctx->hal, WDT_STAGE1, config->timeout_ms * (2 * 1000 / TWDT_TICKS_PER_US), WDT_STAGE_ACTION_RESET_SYSTEM);
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// No need to enable to enable the WDT here, it will be enabled with `esp_task_wdt_impl_timer_restart`
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wdt_hal_write_protect_enable(&ctx->hal);
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/* Return the implementation context to the caller */
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*obj = (twdt_ctx_t) ctx;
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#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_TIMER_SUPPORT_SLEEP_RETENTION
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esp_task_wdt_retention_enable(TWDT_TIMER_GROUP);
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#endif
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}
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return ret;
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}
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esp_err_t esp_task_wdt_impl_timer_reconfigure(twdt_ctx_t obj, const esp_task_wdt_config_t *config)
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{
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esp_err_t ret = ESP_OK;
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twdt_ctx_hard_t* ctx = (twdt_ctx_hard_t*) obj;
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if (config == NULL || ctx == NULL) {
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ret = ESP_ERR_INVALID_STATE;
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}
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if (ret == ESP_OK) {
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wdt_hal_write_protect_disable(&ctx->hal);
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/* Reconfigure the 1st and 2nd stage timeout */
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wdt_hal_config_stage(&ctx->hal, WDT_STAGE0, config->timeout_ms * (1000 / TWDT_TICKS_PER_US), WDT_STAGE_ACTION_INT);
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wdt_hal_config_stage(&ctx->hal, WDT_STAGE1, config->timeout_ms * (2 * 1000 / TWDT_TICKS_PER_US), WDT_STAGE_ACTION_RESET_SYSTEM);
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wdt_hal_write_protect_enable(&ctx->hal);
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}
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return ret;
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}
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void esp_task_wdt_impl_timer_free(twdt_ctx_t obj)
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{
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twdt_ctx_hard_t* ctx = (twdt_ctx_hard_t*) obj;
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if (ctx != NULL) {
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/* Stop hardware timer and the interrupt associated */
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wdt_hal_deinit(&ctx->hal);
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ESP_ERROR_CHECK(esp_intr_disable(ctx->intr_handle));
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/* Disable the Timer Group module */
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PERIPH_RCC_RELEASE_ATOMIC(TWDT_PERIPH_MODULE, ref_count) {
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if (ref_count == 0) {
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timer_ll_enable_bus_clock(TWDT_TIMER_GROUP, false);
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}
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}
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/* Deregister interrupt */
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ESP_ERROR_CHECK(esp_intr_free(ctx->intr_handle));
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#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_TIMER_SUPPORT_SLEEP_RETENTION
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ESP_ERROR_CHECK(esp_task_wdt_retention_disable(TWDT_TIMER_GROUP));
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#endif
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}
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}
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esp_err_t esp_task_wdt_impl_timer_feed(twdt_ctx_t obj)
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{
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esp_err_t ret = ESP_OK;
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twdt_ctx_hard_t* ctx = (twdt_ctx_hard_t*) obj;
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if (ctx == NULL) {
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ret = ESP_ERR_INVALID_STATE;
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}
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if (ret == ESP_OK) {
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wdt_hal_write_protect_disable(&ctx->hal);
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wdt_hal_feed(&ctx->hal);
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wdt_hal_write_protect_enable(&ctx->hal);
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}
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return ret;
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}
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void esp_task_wdt_impl_timeout_triggered(twdt_ctx_t obj)
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{
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twdt_ctx_hard_t* ctx = (twdt_ctx_hard_t*) obj;
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if (ctx != NULL) {
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/* Reset hardware timer so that 2nd stage timeout is not reached (will trigger system reset) */
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wdt_hal_write_protect_disable(&ctx->hal);
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wdt_hal_handle_intr(&ctx->hal); // Feeds WDT and clears acknowledges interrupt
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wdt_hal_write_protect_enable(&ctx->hal);
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}
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}
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esp_err_t esp_task_wdt_impl_timer_stop(twdt_ctx_t obj)
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{
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esp_err_t ret = ESP_OK;
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twdt_ctx_hard_t* ctx = (twdt_ctx_hard_t*) obj;
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if (ctx == NULL) {
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ret = ESP_ERR_INVALID_STATE;
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}
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if (ret == ESP_OK) {
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wdt_hal_write_protect_disable(&ctx->hal);
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wdt_hal_disable(&ctx->hal);
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wdt_hal_write_protect_enable(&ctx->hal);
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}
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return ret;
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}
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esp_err_t esp_task_wdt_impl_timer_restart(twdt_ctx_t obj)
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{
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esp_err_t ret = ESP_OK;
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twdt_ctx_hard_t* ctx = (twdt_ctx_hard_t*) obj;
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if (ctx == NULL) {
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ret = ESP_ERR_INVALID_STATE;
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}
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if (ret == ESP_OK) {
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wdt_hal_write_protect_disable(&ctx->hal);
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wdt_hal_enable(&ctx->hal);
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wdt_hal_feed(&ctx->hal);
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wdt_hal_write_protect_enable(&ctx->hal);
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}
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return ret;
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}
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