mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
a5d5ee7445
This commit deprecates the "freertos/xtensa_context.h" and "xtensa/xtensa_context.h" include paths. Users should use "xtensa_context.h" instead. - Replace legacy include paths - Removed some unnecessary includes of "xtensa_api.h" - Add warning to compatibility header
472 lines
16 KiB
C
472 lines
16 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "xtensa_context.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "esp_debug_helpers.h"
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#include "esp_private/panic_internal.h"
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#include "esp_private/panic_reason.h"
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#include "soc/soc.h"
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#include "esp_private/cache_err_int.h"
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#include "sdkconfig.h"
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#if !CONFIG_IDF_TARGET_ESP32
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#include "soc/extmem_reg.h"
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#include "soc/ext_mem_defs.h"
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#include "soc/rtc_cntl_reg.h"
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#if CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
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#ifdef CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/memprot.h"
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#else
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#include "esp_memprot.h"
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#endif
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#endif
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#endif // CONFIG_IDF_TARGET_ESP32
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void panic_print_registers(const void *f, int core)
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{
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XtExcFrame *frame = (XtExcFrame *) f;
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int *regs = (int *)frame;
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(void)regs;
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const char *sdesc[] = {
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"PC ", "PS ", "A0 ", "A1 ", "A2 ", "A3 ", "A4 ", "A5 ",
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"A6 ", "A7 ", "A8 ", "A9 ", "A10 ", "A11 ", "A12 ", "A13 ",
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"A14 ", "A15 ", "SAR ", "EXCCAUSE", "EXCVADDR", "LBEG ", "LEND ", "LCOUNT "
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};
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/* only dump registers for 'real' crashes, if crashing via abort()
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the register window is no longer useful.
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*/
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panic_print_str("Core ");
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panic_print_dec(core);
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panic_print_str(" register dump:");
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for (int x = 0; x < 24; x += 4) {
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panic_print_str("\r\n");
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for (int y = 0; y < 4; y++) {
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if (sdesc[x + y][0] != 0) {
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panic_print_str(sdesc[x + y]);
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panic_print_str(": 0x");
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panic_print_hex(regs[x + y + 1]);
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panic_print_str(" ");
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}
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}
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}
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// If the core which triggers the interrupt watchpoint was in ISR context, dump the epc registers.
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if (xPortInterruptedFromISRContext()
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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&& ((core == 0 && frame->exccause == PANIC_RSN_INTWDT_CPU0) ||
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(core == 1 && frame->exccause == PANIC_RSN_INTWDT_CPU1))
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#endif //!CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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) {
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panic_print_str("\r\n");
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uint32_t __value;
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panic_print_str("Core ");
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panic_print_dec(core);
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panic_print_str(" was running in ISR context:\r\n");
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__asm__("rsr.epc1 %0" : "=a"(__value));
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panic_print_str("EPC1 : 0x");
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panic_print_hex(__value);
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__asm__("rsr.epc2 %0" : "=a"(__value));
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panic_print_str(" EPC2 : 0x");
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panic_print_hex(__value);
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__asm__("rsr.epc3 %0" : "=a"(__value));
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panic_print_str(" EPC3 : 0x");
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panic_print_hex(__value);
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__asm__("rsr.epc4 %0" : "=a"(__value));
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panic_print_str(" EPC4 : 0x");
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panic_print_hex(__value);
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}
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}
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static void print_illegal_instruction_details(const void *f)
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{
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XtExcFrame *frame = (XtExcFrame *) f;
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/* Print out memory around the instruction word */
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uint32_t epc = frame->pc;
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epc = (epc & ~0x3) - 4;
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/* check that the address was sane */
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if (epc < SOC_IROM_MASK_LOW || epc >= SOC_IROM_HIGH) {
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return;
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}
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volatile uint32_t *pepc = (uint32_t *)epc;
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(void)pepc;
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panic_print_str("Memory dump at 0x");
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panic_print_hex(epc);
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panic_print_str(": ");
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panic_print_hex(*pepc);
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panic_print_str(" ");
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panic_print_hex(*(pepc + 1));
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panic_print_str(" ");
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panic_print_hex(*(pepc + 2));
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}
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static void print_debug_exception_details(const void *f)
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{
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int debug_rsn;
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asm("rsr.debugcause %0":"=r"(debug_rsn));
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panic_print_str("Debug exception reason: ");
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if (debug_rsn & XCHAL_DEBUGCAUSE_ICOUNT_MASK) {
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panic_print_str("SingleStep ");
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}
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if (debug_rsn & XCHAL_DEBUGCAUSE_IBREAK_MASK) {
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panic_print_str("HwBreakpoint ");
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}
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if (debug_rsn & XCHAL_DEBUGCAUSE_DBREAK_MASK) {
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//Unlike what the ISA manual says, this core seemingly distinguishes from a DBREAK
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//reason caused by watchdog 0 and one caused by watchdog 1 by setting bit 8 of the
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//debugcause if the cause is watchpoint 1 and clearing it if it's watchpoint 0.
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if (debug_rsn & (1 << 8)) {
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#if CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK
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int core = 0;
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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if (f == g_exc_frames[1]) {
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core = 1;
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}
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#endif
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const char *name = pcTaskGetName(xTaskGetCurrentTaskHandleForCore(core));
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panic_print_str("Stack canary watchpoint triggered (");
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panic_print_str(name);
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panic_print_str(") ");
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#else
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panic_print_str("Watchpoint 1 triggered ");
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#endif
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} else {
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panic_print_str("Watchpoint 0 triggered ");
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}
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}
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if (debug_rsn & XCHAL_DEBUGCAUSE_BREAK_MASK) {
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panic_print_str("BREAK instr ");
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}
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if (debug_rsn & XCHAL_DEBUGCAUSE_BREAKN_MASK) {
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panic_print_str("BREAKN instr ");
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}
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if (debug_rsn & XCHAL_DEBUGCAUSE_DEBUGINT_MASK) {
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panic_print_str("DebugIntr ");
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}
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}
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#if CONFIG_IDF_TARGET_ESP32S2
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static inline void print_cache_err_details(const void *f)
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{
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uint32_t vaddr = 0, size = 0;
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uint32_t status[2];
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status[0] = REG_READ(EXTMEM_CACHE_DBG_STATUS0_REG);
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status[1] = REG_READ(EXTMEM_CACHE_DBG_STATUS1_REG);
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for (int i = 0; i < 32; i++) {
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switch (status[0] & BIT(i)) {
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case EXTMEM_IC_SYNC_SIZE_FAULT_ST:
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vaddr = REG_READ(EXTMEM_PRO_ICACHE_MEM_SYNC0_REG);
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size = REG_READ(EXTMEM_PRO_ICACHE_MEM_SYNC1_REG);
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panic_print_str("Icache sync parameter configuration error, the error address and size is 0x");
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panic_print_hex(vaddr);
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panic_print_str("(0x");
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panic_print_hex(size);
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panic_print_str(")\r\n");
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break;
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case EXTMEM_IC_PRELOAD_SIZE_FAULT_ST:
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vaddr = REG_READ(EXTMEM_PRO_ICACHE_PRELOAD_ADDR_REG);
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size = REG_READ(EXTMEM_PRO_ICACHE_PRELOAD_SIZE_REG);
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panic_print_str("Icache preload parameter configuration error, the error address and size is 0x");
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panic_print_hex(vaddr);
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panic_print_str("(0x");
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panic_print_hex(size);
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panic_print_str(")\r\n");
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break;
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case EXTMEM_ICACHE_REJECT_ST:
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vaddr = REG_READ(EXTMEM_PRO_ICACHE_REJECT_VADDR_REG);
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panic_print_str("Icache reject error occurred while accessing the address 0x");
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panic_print_hex(vaddr);
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if (REG_READ(EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_REG) & SOC_MMU_INVALID) {
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panic_print_str(" (invalid mmu entry)");
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}
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panic_print_str("\r\n");
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break;
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default:
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break;
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}
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switch (status[1] & BIT(i)) {
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case EXTMEM_DC_SYNC_SIZE_FAULT_ST:
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vaddr = REG_READ(EXTMEM_PRO_DCACHE_MEM_SYNC0_REG);
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size = REG_READ(EXTMEM_PRO_DCACHE_MEM_SYNC1_REG);
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panic_print_str("Dcache sync parameter configuration error, the error address and size is 0x");
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panic_print_hex(vaddr);
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panic_print_str("(0x");
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panic_print_hex(size);
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panic_print_str(")\r\n");
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break;
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case EXTMEM_DC_PRELOAD_SIZE_FAULT_ST:
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vaddr = REG_READ(EXTMEM_PRO_DCACHE_PRELOAD_ADDR_REG);
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size = REG_READ(EXTMEM_PRO_DCACHE_PRELOAD_SIZE_REG);
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panic_print_str("Dcache preload parameter configuration error, the error address and size is 0x");
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panic_print_hex(vaddr);
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panic_print_str("(0x");
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panic_print_hex(size);
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panic_print_str(")\r\n");
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break;
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case EXTMEM_DCACHE_WRITE_FLASH_ST:
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panic_print_str("Write back error occurred while dcache tries to write back to flash\r\n");
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break;
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case EXTMEM_DCACHE_REJECT_ST:
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vaddr = REG_READ(EXTMEM_PRO_DCACHE_REJECT_VADDR_REG);
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panic_print_str("Dcache reject error occurred while accessing the address 0x");
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panic_print_hex(vaddr);
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if (REG_READ(EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_REG) & SOC_MMU_INVALID) {
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panic_print_str(" (invalid mmu entry)");
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}
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panic_print_str("\r\n");
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break;
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case EXTMEM_MMU_ENTRY_FAULT_ST:
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vaddr = REG_READ(EXTMEM_PRO_CACHE_MMU_FAULT_VADDR_REG);
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panic_print_str("MMU entry fault error occurred while accessing the address 0x");
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panic_print_hex(vaddr);
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if (REG_READ(EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_REG) & SOC_MMU_INVALID) {
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panic_print_str(" (invalid mmu entry)");
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}
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panic_print_str("\r\n");
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break;
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default:
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break;
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}
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}
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}
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#if CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
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#define MEMPROT_OP_INVALID 0xFFFFFFFF
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static inline void print_memprot_err_details(const void *f)
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{
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uint32_t *fault_addr;
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uint32_t op_type = MEMPROT_OP_INVALID, op_subtype;
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const char *operation_type;
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mem_type_prot_t mem_type = esp_memprot_get_active_intr_memtype();
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if (mem_type != MEMPROT_NONE) {
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if (esp_memprot_get_fault_status(mem_type, &fault_addr, &op_type, &op_subtype) != ESP_OK) {
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op_type = MEMPROT_OP_INVALID;
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}
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}
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if (op_type == MEMPROT_OP_INVALID) {
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operation_type = "Unknown";
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fault_addr = (uint32_t *)MEMPROT_OP_INVALID;
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} else {
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if (op_type == 0) {
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operation_type = (mem_type == MEMPROT_IRAM0_SRAM && op_subtype == 0) ? "Instruction fetch" : "Read";
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} else {
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operation_type = "Write";
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}
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}
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panic_print_str(operation_type);
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panic_print_str(" operation at address 0x");
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panic_print_hex((uint32_t)fault_addr);
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panic_print_str(" not permitted (");
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panic_print_str(esp_memprot_type_to_str(mem_type));
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panic_print_str(")\r\n");
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}
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#endif
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#elif CONFIG_IDF_TARGET_ESP32S3
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static inline void print_cache_err_details(const void *f)
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{
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uint32_t vaddr = 0, size = 0;
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uint32_t status;
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status = REG_READ(EXTMEM_CACHE_ILG_INT_ST_REG);
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for (int i = 0; i < 32; i++) {
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switch (status & BIT(i)) {
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case EXTMEM_ICACHE_SYNC_OP_FAULT_ST:
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//TODO, which size should fetch
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//vaddr = REG_READ(EXTMEM_ICACHE_MEM_SYNC0_REG);
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//size = REG_READ(EXTMEM_ICACHE_MEM_SYNC1_REG);
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panic_print_str("Icache sync parameter configuration error, the error address and size is 0x");
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panic_print_hex(vaddr);
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panic_print_str("(0x");
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panic_print_hex(size);
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panic_print_str(")\r\n");
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break;
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case EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST:
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//TODO, which size should fetch
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vaddr = REG_READ(EXTMEM_ICACHE_PRELOAD_ADDR_REG);
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size = REG_READ(EXTMEM_ICACHE_PRELOAD_SIZE_REG);
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panic_print_str("Icache preload parameter configuration error, the error address and size is 0x");
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panic_print_hex(vaddr);
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panic_print_str("(0x");
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panic_print_hex(size);
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panic_print_str(")\r\n");
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break;
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case EXTMEM_DCACHE_SYNC_OP_FAULT_ST:
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//TODO, which size should fetch
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//vaddr = REG_READ(EXTMEM_DCACHE_MEM_SYNC0_REG);
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//size = REG_READ(EXTMEM_DCACHE_MEM_SYNC1_REG);
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panic_print_str("Dcache sync parameter configuration error, the error address and size is 0x");
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panic_print_hex(vaddr);
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panic_print_str("(0x");
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panic_print_hex(size);
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panic_print_str(")\r\n");
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break;
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case EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST:
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//TODO, which size should fetch
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vaddr = REG_READ(EXTMEM_DCACHE_PRELOAD_ADDR_REG);
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size = REG_READ(EXTMEM_DCACHE_PRELOAD_SIZE_REG);
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panic_print_str("Dcache preload parameter configuration error, the error address and size is 0x");
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panic_print_hex(vaddr);
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panic_print_str("(0x");
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panic_print_hex(size);
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panic_print_str(")\r\n");
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break;
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case EXTMEM_DCACHE_WRITE_FLASH_ST:
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panic_print_str("Write back error occurred while dcache tries to write back to flash\r\n");
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break;
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case EXTMEM_MMU_ENTRY_FAULT_ST:
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vaddr = REG_READ(EXTMEM_CACHE_MMU_FAULT_VADDR_REG);
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panic_print_str("MMU entry fault error occurred while accessing the address 0x");
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panic_print_hex(vaddr);
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if (REG_READ(EXTMEM_CACHE_MMU_FAULT_CONTENT_REG) & SOC_MMU_INVALID) {
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panic_print_str(" (invalid mmu entry)");
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}
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panic_print_str("\r\n");
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break;
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default:
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break;
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}
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}
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panic_print_str("\r\n");
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}
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#endif
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void panic_arch_fill_info(void *f, panic_info_t *info)
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{
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XtExcFrame *frame = (XtExcFrame *) f;
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static const char *reason[] = {
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"IllegalInstruction", "Syscall", "InstructionFetchError", "LoadStoreError",
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"Level1Interrupt", "Alloca", "IntegerDivideByZero", "PCValue",
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"Privileged", "LoadStoreAlignment", "res", "res",
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"InstrPDAddrError", "LoadStorePIFDataError", "InstrPIFAddrError", "LoadStorePIFAddrError",
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"InstTLBMiss", "InstTLBMultiHit", "InstFetchPrivilege", "res",
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"InstrFetchProhibited", "res", "res", "res",
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"LoadStoreTLBMiss", "LoadStoreTLBMultihit", "LoadStorePrivilege", "res",
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"LoadProhibited", "StoreProhibited", "res", "res",
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"Cp0Dis", "Cp1Dis", "Cp2Dis", "Cp3Dis",
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"Cp4Dis", "Cp5Dis", "Cp6Dis", "Cp7Dis"
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};
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if (frame->exccause < (sizeof(reason) / sizeof(char *))) {
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info->reason = (reason[frame->exccause]);
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} else {
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info->reason = "Unknown";
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}
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info->description = "Exception was unhandled.";
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if (frame->exccause == EXCCAUSE_ILLEGAL) {
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info->details = print_illegal_instruction_details;
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}
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info->addr = ((void *) ((XtExcFrame *) frame)->pc);
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}
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void panic_soc_fill_info(void *f, panic_info_t *info)
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{
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// [refactor-todo] this should be in the common port panic_handler.c, once
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// these special exceptions are supported in there.
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XtExcFrame *frame = (XtExcFrame *) f;
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if (frame->exccause == PANIC_RSN_INTWDT_CPU0) {
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info->core = 0;
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info->exception = PANIC_EXCEPTION_IWDT;
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} else if (frame->exccause == PANIC_RSN_INTWDT_CPU1) {
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info->core = 1;
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info->exception = PANIC_EXCEPTION_IWDT;
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} else if (frame->exccause == PANIC_RSN_CACHEERR) {
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info->core = esp_cache_err_get_cpuid();
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} else {}
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//Please keep in sync with PANIC_RSN_* defines
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static const char *pseudo_reason[] = {
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"Unknown reason",
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"Unhandled debug exception",
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"Double exception",
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"Unhandled kernel exception",
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"Coprocessor exception",
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"Interrupt wdt timeout on CPU0",
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"Interrupt wdt timeout on CPU1",
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"Cache disabled but cached memory region accessed",
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};
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info->reason = pseudo_reason[0];
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info->description = NULL;
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if (frame->exccause <= PANIC_RSN_MAX) {
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info->reason = pseudo_reason[frame->exccause];
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}
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if (frame->exccause == PANIC_RSN_DEBUGEXCEPTION) {
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info->details = print_debug_exception_details;
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info->exception = PANIC_EXCEPTION_DEBUG;
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}
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//MV note: ESP32S3 PMS handling?
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#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
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if (frame->exccause == PANIC_RSN_CACHEERR) {
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#if CONFIG_ESP_SYSTEM_MEMPROT_FEATURE && CONFIG_IDF_TARGET_ESP32S2
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if ( esp_memprot_is_intr_ena_any() ) {
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info->details = print_memprot_err_details;
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info->reason = "Memory protection fault";
|
|
} else
|
|
#endif
|
|
{
|
|
info->details = print_cache_err_details;
|
|
}
|
|
}
|
|
#endif
|
|
}
|
|
|
|
uint32_t panic_get_address(const void *f)
|
|
{
|
|
return ((XtExcFrame *)f)->pc;
|
|
}
|
|
|
|
uint32_t panic_get_cause(const void *f)
|
|
{
|
|
return ((XtExcFrame *)f)->exccause;
|
|
}
|
|
|
|
void panic_set_address(void *f, uint32_t addr)
|
|
{
|
|
((XtExcFrame *)f)->pc = addr;
|
|
}
|
|
|
|
void panic_print_backtrace(const void *f, int core)
|
|
{
|
|
XtExcFrame *xt_frame = (XtExcFrame *) f;
|
|
esp_backtrace_frame_t frame = {.pc = xt_frame->pc, .sp = xt_frame->a1, .next_pc = xt_frame->a0, .exc_frame = xt_frame};
|
|
esp_backtrace_print_from_frame(100, &frame, true);
|
|
}
|