mirror of
https://github.com/espressif/esp-idf.git
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213 lines
6.6 KiB
C
213 lines
6.6 KiB
C
/*
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* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "esp_err.h"
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#include "soc/soc_caps.h"
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#include "hal/dma_types.h"
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#include "hal/adc_types.h"
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#include "hal/adc_hal_common.h"
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#if SOC_ADC_DMA_SUPPORTED
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#include "hal/adc_ll.h"
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#endif
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#if SOC_GDMA_SUPPORTED
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#include "hal/gdma_ll.h"
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#endif
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#if CONFIG_IDF_TARGET_ESP32S2
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//ADC utilises SPI3 DMA on ESP32S2
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#include "hal/spi_ll.h"
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#endif
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#if CONFIG_IDF_TARGET_ESP32
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//ADC utilises I2S0 DMA on ESP32
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#include "hal/i2s_ll.h"
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if SOC_GDMA_SUPPORTED
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#define ADC_HAL_DMA_INTR_MASK GDMA_LL_EVENT_RX_SUC_EOF
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#elif CONFIG_IDF_TARGET_ESP32S2
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#define ADC_HAL_DMA_INTR_MASK SPI_LL_INTR_IN_SUC_EOF
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#else //CONFIG_IDF_TARGET_ESP32
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#define ADC_HAL_DMA_INTR_MASK BIT(9)
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#endif
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/**
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* @brief Enum for DMA descriptor status
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*/
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typedef enum adc_hal_dma_desc_status_t {
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ADC_HAL_DMA_DESC_VALID = 0, ///< This DMA descriptor is written by HW already
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ADC_HAL_DMA_DESC_WAITING = 1, ///< This DMA descriptor is not written by HW yet
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ADC_HAL_DMA_DESC_NULL = 2 ///< This DMA descriptor is NULL
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} adc_hal_dma_desc_status_t;
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/**
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* @brief Configuration of the HAL
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*/
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typedef struct adc_hal_dma_config_t {
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void *dev; ///< DMA peripheral address
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uint32_t eof_desc_num; ///< Number of dma descriptors that is eof
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uint32_t eof_step; ///< Number of linked descriptors that is one eof
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uint32_t dma_chan; ///< DMA channel to be used
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uint32_t eof_num; ///< Bytes between 2 in_suc_eof interrupts
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} adc_hal_dma_config_t;
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/**
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* @brief Context of the HAL
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*/
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typedef struct adc_hal_dma_ctx_t {
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/**< this needs to be malloced by the driver layer first */
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dma_descriptor_t *rx_desc; ///< DMA descriptors
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/**< these will be assigned by hal layer itself */
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dma_descriptor_t desc_dummy_head; ///< Dummy DMA descriptor for ``cur_desc_ptr`` to start
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dma_descriptor_t *cur_desc_ptr; ///< Pointer to the current descriptor
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/**< these need to be configured by `adc_hal_dma_config_t` via driver layer*/
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void *dev; ///< DMA address
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uint32_t eof_desc_num; ///< Number of dma descriptors that is eof
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uint32_t eof_step; ///< Number of linked descriptors that is one eof
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uint32_t dma_chan; ///< DMA channel to be used
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uint32_t eof_num; ///< Words between 2 in_suc_eof interrupts
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} adc_hal_dma_ctx_t;
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typedef struct adc_hal_digi_ctrlr_cfg_t {
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uint32_t adc_pattern_len; //total pattern item number, including ADC1 and ADC2
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adc_digi_pattern_config_t *adc_pattern; //pattern item
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uint32_t sample_freq_hz; //ADC sample frequency
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adc_digi_convert_mode_t conv_mode; //controller work mode
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uint32_t bit_width; //output data width
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adc_continuous_clk_src_t clk_src; ///< Clock source
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uint32_t clk_src_freq_hz; ///< Clock source frequency in hz
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} adc_hal_digi_ctrlr_cfg_t;
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/*---------------------------------------------------------------
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PWDET(Power detect) controller setting
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---------------------------------------------------------------*/
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/**
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* Set adc cct for PWDET controller.
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*
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* @note Capacitor tuning of the PA power monitor. cct set to the same value with PHY.
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* @prarm cct Range: 0 ~ 7.
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*/
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#define adc_hal_pwdet_set_cct(cct) adc_ll_pwdet_set_cct(cct)
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/**
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* Get adc cct for PWDET controller.
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*
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* @note Capacitor tuning of the PA power monitor. cct set to the same value with PHY.
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* @return cct Range: 0 ~ 7.
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*/
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#define adc_hal_pwdet_get_cct() adc_ll_pwdet_get_cct()
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/*---------------------------------------------------------------
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Digital controller setting
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---------------------------------------------------------------*/
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/**
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* @brief Initialize the HW
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*
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* @param hal Context of the HAL
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*/
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void adc_hal_digi_init(adc_hal_dma_ctx_t *hal);
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/**
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* Digital controller deinitialization.
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*
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* @param hal Context of the HAL
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*/
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void adc_hal_digi_deinit(adc_hal_dma_ctx_t *hal);
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/**
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* @brief Initialize the hal context
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*
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* @param hal Context of the HAL
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* @param config Configuration of the HAL
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*/
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void adc_hal_dma_ctx_config(adc_hal_dma_ctx_t *hal, const adc_hal_dma_config_t *config);
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/**
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* Setting the digital controller.
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*
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* @param hal Context of the HAL
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* @param cfg Pointer to digital controller paramter.
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*/
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void adc_hal_digi_controller_config(adc_hal_dma_ctx_t *hal, const adc_hal_digi_ctrlr_cfg_t *cfg);
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/**
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* @brief Start Conversion
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*
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* @param hal Context of the HAL
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* @param data_buf Pointer to the data buffer, the length should be multiple of ``desc_max_num`` and ``eof_num`` in ``adc_hal_dma_ctx_t``
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*/
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void adc_hal_digi_start(adc_hal_dma_ctx_t *hal, uint8_t *data_buf);
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#if !SOC_GDMA_SUPPORTED
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/**
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* @brief Get the DMA descriptor that Hardware has finished processing.
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*
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* @param hal Context of the HAL
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*
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* @return DMA descriptor address
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*/
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intptr_t adc_hal_get_desc_addr(adc_hal_dma_ctx_t *hal);
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/**
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* @brief Check the hardware interrupt event
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*
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* @param hal Context of the HAL
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* @param mask Event mask
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*
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* @return True: the event is triggered. False: the event is not triggered yet.
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*/
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bool adc_hal_check_event(adc_hal_dma_ctx_t *hal, uint32_t mask);
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#endif
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/**
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* @brief Get the ADC reading result
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*
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* @param hal Context of the HAL
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* @param eof_desc_addr The last descriptor that is finished by HW. Should be got from DMA
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* @param[out] buffer ADC reading result buffer
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* @param[out] len ADC reading result len
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*
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* @return See ``adc_hal_dma_desc_status_t``
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*/
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adc_hal_dma_desc_status_t adc_hal_get_reading_result(adc_hal_dma_ctx_t *hal, const intptr_t eof_desc_addr, uint8_t **buffer, uint32_t *len);
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/**
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* @brief Clear interrupt
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*
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* @param hal Context of the HAL
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* @param mask mask of the interrupt
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*/
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void adc_hal_digi_clr_intr(adc_hal_dma_ctx_t *hal, uint32_t mask);
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/**
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* @brief Enable interrupt
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*
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* @param hal Context of the HAL
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* @param mask mask of the interrupt
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*/
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void adc_hal_digi_dis_intr(adc_hal_dma_ctx_t *hal, uint32_t mask);
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/**
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* @brief Stop conversion
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*
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* @param hal Context of the HAL
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*/
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void adc_hal_digi_stop(adc_hal_dma_ctx_t *hal);
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#ifdef __cplusplus
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}
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#endif
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