esp-idf/components/soc/linker.lf
Darian Leung fb2d6a44eb CAN: ISR runs when cache is disabled
This commit adds the feature where the CAN ISR will continue to
run even if the cache is disabled. Whilst cache is disabled, any
received messages will go into the RX queue, and any pending TX
messages in the TX queue will be transmitted. This feature should
be enabled using the CONFIG_CAN_ISR_IN_IRAM option.
2021-03-09 08:47:58 +08:00

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[mapping:soc]
archive: libsoc.a
entries:
cpu_util (noflash_text)
rtc_clk (noflash)
rtc_clk_init (noflash_text)
rtc_init (noflash_text)
rtc_periph (noflash_text)
rtc_pm (noflash_text)
rtc_sleep (noflash_text)
rtc_time (noflash_text)
rtc_wdt (noflash_text)
spi_hal_iram (noflash_text)
spi_slave_hal_iram (noflash_text)
if UART_ISR_IN_IRAM = y:
uart_hal_iram (noflash_text)
else:
uart_hal_iram (default)
spi_flash_hal_iram (noflash)
ledc_hal_iram (noflash_text)
i2c_hal_iram (noflash)
spi_flash_hal_gpspi (noflash)
lldesc (noflash_text)
if CAN_ISR_IN_IRAM = y:
can_hal_iram (noflash)
else:
can_hal_iram (default)