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https://github.com/espressif/esp-idf.git
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e3191df37a
change(xtensa): Deprecate legacy include paths Closes IDF-7230 See merge request espressif/esp-idf!26725
136 lines
4.1 KiB
ArmAsm
136 lines
4.1 KiB
ArmAsm
/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <xtensa/coreasm.h>
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#include <xtensa/corebits.h>
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#include <xtensa/config/system.h>
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#include "xtensa_context.h"
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#include "esp_private/panic_reason.h"
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#include "sdkconfig.h"
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#include "soc/soc.h"
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#include "soc/dport_reg.h"
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#include "soc/soc_caps.h"
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/*
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Interrupt , a high-priority interrupt, is used for several things:
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- IPC_ISR handler
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- Cache error panic handler
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- Interrupt watchdog panic handler
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*/
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#define L4_INTR_STACK_SIZE 12
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#define L4_INTR_A2_OFFSET 0
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#define L4_INTR_A3_OFFSET 4
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#define L4_INTR_A4_OFFSET 8
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.data
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_l4_intr_stack:
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.space L4_INTR_STACK_SIZE*SOC_CPU_CORES_NUM /* This allocates stacks for each individual CPU. */
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.section .iram1,"ax"
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.global xt_highint4
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.type xt_highint4,@function
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.align 4
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xt_highint4:
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#ifndef CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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/* See if we're here for the IPC_ISR interrupt */
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rsr a0, INTERRUPT
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extui a0, a0, ETS_IPC_ISR_INUM, 1
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bnez a0, jump_to_esp_ipc_isr_handler
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#endif // not CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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/* Allocate exception frame and save minimal context. */
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mov a0, sp
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addi sp, sp, -XT_STK_FRMSZ
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s32i a0, sp, XT_STK_A1
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#if XCHAL_HAVE_WINDOWED
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s32e a0, sp, -12 /* for debug backtrace */
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#endif
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rsr a0, PS /* save interruptee's PS */
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s32i a0, sp, XT_STK_PS
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rsr a0, EPC_4 /* save interruptee's PC */
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s32i a0, sp, XT_STK_PC
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rsr a0, EXCSAVE_4 /* save interruptee's a0 */
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s32i a0, sp, XT_STK_A0
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#if XCHAL_HAVE_WINDOWED
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s32e a0, sp, -16 /* for debug backtrace */
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#endif
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s32i a12, sp, XT_STK_A12 /* _xt_context_save requires A12- */
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s32i a13, sp, XT_STK_A13 /* A13 to have already been saved */
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call0 _xt_context_save
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/* Save vaddr into exception frame */
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rsr a0, EXCVADDR
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s32i a0, sp, XT_STK_EXCVADDR
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/* Figure out reason, save into EXCCAUSE reg */
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rsr a0, INTERRUPT
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extui a0, a0, ETS_CACHEERR_INUM, 1 /* get cacheerr int bit */
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beqz a0, 1f
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/* Kill this interrupt; we cannot reset it. */
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rsr a0, INTENABLE
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movi a4, ~(1<<ETS_CACHEERR_INUM)
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and a0, a4, a0
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wsr a0, INTENABLE
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movi a0, PANIC_RSN_CACHEERR
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j 9f
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1:
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#if CONFIG_ESP_INT_WDT_CHECK_CPU1
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/* Check if the cause is the app cpu failing to tick.*/
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movi a0, int_wdt_cpu1_ticked
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l32i a0, a0, 0
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bnez a0, 2f
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/* It is. Modify cause. */
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movi a0,PANIC_RSN_INTWDT_CPU1
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j 9f
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2:
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#endif
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/* Set EXCCAUSE to reflect cause of the wdt int trigger */
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movi a0,PANIC_RSN_INTWDT_CPU0
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9:
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/* Found the reason, now save it. */
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s32i a0, sp, XT_STK_EXCCAUSE
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/* Set up PS for C, disable all interrupts except NMI and debug, and clear EXCM. */
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movi a0, PS_INTLEVEL(5) | PS_UM | PS_WOE
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wsr a0, PS
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//Call panic handler
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mov a6,sp
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call4 panicHandler
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call0 _xt_context_restore
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l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */
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wsr a0, PS
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l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */
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wsr a0, EPC_4
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l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */
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l32i sp, sp, XT_STK_A1 /* remove exception frame */
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rsync /* ensure PS and EPC written */
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rsr a0, EXCSAVE_4 /* restore a0 */
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rfi 4
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#ifdef CONFIG_ESP_IPC_ISR_ENABLE
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jump_to_esp_ipc_isr_handler:
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/* Address of `esp_ipc_isr_handler_address` will always be in `movi` range
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* as it is defined right above. */
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movi a0, esp_ipc_isr_handler
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jx a0
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#endif
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/* The linker has no reason to link in this file; all symbols it exports are already defined
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(weakly!) in the default int handler. Define a symbol here so we can use it to have the
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linker inspect this anyway. */
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.global ld_include_highint_hdl
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ld_include_highint_hdl:
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