mirror of
https://github.com/espressif/esp-idf.git
synced 2024-09-19 14:26:01 -04:00
631e15c6eb
If LDO1 is used by spi flash, then we recommend to give the ownership to the hardware. Software just read the parameters from the efuse and set to PMU.
209 lines
6.4 KiB
C
209 lines
6.4 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <freertos/FreeRTOS.h>
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#include "clk_ctrl_os.h"
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#include "soc/rtc.h"
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#include "esp_ldo_regulator.h"
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#include "esp_private/esp_clk_tree_common.h"
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#include "esp_check.h"
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#include "hal/clk_tree_hal.h"
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#include "hal/clk_tree_ll.h"
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#if SOC_CLK_MPLL_SUPPORTED
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#include "rtc_clk.h"
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#endif
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#if SOC_CLK_APLL_SUPPORTED || SOC_CLK_MPLL_SUPPORTED
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static const char *TAG = "clk_ctrl_os";
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#endif
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static portMUX_TYPE periph_spinlock = portMUX_INITIALIZER_UNLOCKED;
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static uint8_t s_periph_ref_counts = 0;
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static uint32_t s_rc_fast_freq = 0; // Frequency of the RC_FAST clock in Hz
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#if SOC_CLK_APLL_SUPPORTED
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// Current APLL frequency, in HZ. Zero if APLL is not enabled.
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static uint32_t s_cur_apll_freq = 0;
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static int s_apll_ref_cnt = 0;
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#endif
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#if SOC_CLK_MPLL_SUPPORTED
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static uint32_t s_cur_mpll_freq = 0;
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static int s_mpll_ref_cnt = 0;
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static esp_ldo_channel_handle_t s_ldo_chan = NULL;
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#endif
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bool periph_rtc_dig_clk8m_enable(void)
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{
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portENTER_CRITICAL(&periph_spinlock);
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if (s_periph_ref_counts == 0) {
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rtc_dig_clk8m_enable();
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#if SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
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s_rc_fast_freq = esp_clk_tree_rc_fast_get_freq_hz(ESP_CLK_TREE_SRC_FREQ_PRECISION_EXACT);
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if (s_rc_fast_freq == 0) {
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rtc_dig_clk8m_disable();
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portEXIT_CRITICAL(&periph_spinlock);
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return false;
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}
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#endif //SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
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}
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s_periph_ref_counts++;
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portEXIT_CRITICAL(&periph_spinlock);
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return true;
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}
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uint32_t periph_rtc_dig_clk8m_get_freq(void)
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{
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#if !SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
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/* Workaround: CLK8M calibration cannot be performed, we can only return its theoretic value */
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return SOC_CLK_RC_FAST_FREQ_APPROX;
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#else
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return s_rc_fast_freq;
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#endif
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}
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void periph_rtc_dig_clk8m_disable(void)
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{
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portENTER_CRITICAL(&periph_spinlock);
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assert(s_periph_ref_counts > 0);
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s_periph_ref_counts--;
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if (s_periph_ref_counts == 0) {
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s_rc_fast_freq = 0;
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rtc_dig_clk8m_disable();
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}
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portEXIT_CRITICAL(&periph_spinlock);
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}
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#if SOC_CLK_APLL_SUPPORTED
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void periph_rtc_apll_acquire(void)
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{
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portENTER_CRITICAL(&periph_spinlock);
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s_apll_ref_cnt++;
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if (s_apll_ref_cnt == 1) {
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// For the first time enable APLL, need to set power up
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rtc_clk_apll_enable(true);
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}
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portEXIT_CRITICAL(&periph_spinlock);
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}
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void periph_rtc_apll_release(void)
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{
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portENTER_CRITICAL(&periph_spinlock);
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assert(s_apll_ref_cnt > 0);
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s_apll_ref_cnt--;
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if (s_apll_ref_cnt == 0) {
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// If there is no peripheral using APLL, shut down the power
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s_cur_apll_freq = 0;
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rtc_clk_apll_enable(false);
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}
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portEXIT_CRITICAL(&periph_spinlock);
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}
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esp_err_t periph_rtc_apll_freq_set(uint32_t expt_freq, uint32_t *real_freq)
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{
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uint32_t o_div = 0;
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uint32_t sdm0 = 0;
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uint32_t sdm1 = 0;
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uint32_t sdm2 = 0;
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// Guarantee 'periph_rtc_apll_acquire' has been called before set apll freq
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assert(s_apll_ref_cnt > 0);
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uint32_t apll_freq = rtc_clk_apll_coeff_calc(expt_freq, &o_div, &sdm0, &sdm1, &sdm2);
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ESP_RETURN_ON_FALSE(apll_freq, ESP_ERR_INVALID_ARG, TAG, "APLL coefficients calculate failed");
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bool need_config = true;
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portENTER_CRITICAL(&periph_spinlock);
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/* If APLL is not in use or only one peripheral in use, its frequency can be changed as will
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* But when more than one peripheral refers APLL, its frequency is not allowed to change once it is set */
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if (s_cur_apll_freq == 0 || s_apll_ref_cnt < 2) {
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s_cur_apll_freq = apll_freq;
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} else {
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apll_freq = s_cur_apll_freq;
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need_config = false;
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}
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portEXIT_CRITICAL(&periph_spinlock);
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*real_freq = apll_freq;
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if (need_config) {
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ESP_LOGD(TAG, "APLL will working at %"PRIu32" Hz with coefficients [sdm0] %"PRIu32" [sdm1] %"PRIu32" [sdm2] %"PRIu32" [o_div] %"PRIu32"",
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apll_freq, sdm0, sdm1, sdm2, o_div);
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/* Set coefficients for APLL, notice that it doesn't mean APLL will start */
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rtc_clk_apll_coeff_set(o_div, sdm0, sdm1, sdm2);
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} else {
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return ESP_ERR_INVALID_STATE;
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}
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return ESP_OK;
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}
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#endif // SOC_CLK_APLL_SUPPORTED
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#if SOC_CLK_MPLL_SUPPORTED
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esp_err_t IRAM_ATTR periph_rtc_mpll_acquire(void)
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{
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// power up LDO for the MPLL
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#if CONFIG_ESP_LDO_RESERVE_PSRAM
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esp_ldo_channel_config_t ldo_mpll_config = {
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.chan_id = CONFIG_ESP_LDO_CHAN_PSRAM_DOMAIN,
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.voltage_mv = CONFIG_ESP_LDO_VOLTAGE_PSRAM_DOMAIN,
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};
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ESP_RETURN_ON_ERROR(esp_ldo_acquire_channel(&ldo_mpll_config, &s_ldo_chan), TAG, "acquire internal LDO for MPLL failed");
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#endif
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portENTER_CRITICAL(&periph_spinlock);
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s_mpll_ref_cnt++;
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if (s_mpll_ref_cnt == 1) {
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// For the first time enable MPLL, need to set power up
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rtc_clk_mpll_enable();
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}
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portEXIT_CRITICAL(&periph_spinlock);
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return ESP_OK;
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}
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void periph_rtc_mpll_release(void)
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{
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#if defined(CONFIG_ESP_LDO_CHAN_PSRAM_DOMAIN) && CONFIG_ESP_LDO_CHAN_PSRAM_DOMAIN != -1
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if (s_ldo_chan) {
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esp_ldo_release_channel(s_ldo_chan);
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}
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#endif
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portENTER_CRITICAL(&periph_spinlock);
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assert(s_mpll_ref_cnt > 0);
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s_mpll_ref_cnt--;
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if (s_mpll_ref_cnt == 0) {
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// If there is no peripheral using MPLL, shut down the power
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s_cur_mpll_freq = 0;
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rtc_clk_mpll_disable();
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}
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portEXIT_CRITICAL(&periph_spinlock);
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}
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esp_err_t IRAM_ATTR periph_rtc_mpll_freq_set(uint32_t expt_freq, uint32_t *real_freq)
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{
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esp_err_t ret = ESP_OK;
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// Guarantee 'periph_rtc_apll_acquire' has been called before set apll freq
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assert(s_mpll_ref_cnt > 0);
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portENTER_CRITICAL(&periph_spinlock);
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if (s_cur_mpll_freq == expt_freq) {
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goto end;
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}
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/* If MPLL is not in use or only one peripheral in use, its frequency can be changed as will
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* But when more than one peripheral refers MPLL, its frequency is not allowed to change once it is set */
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if (s_cur_mpll_freq == 0 || s_mpll_ref_cnt < 2) {
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uint32_t xtal_freq_mhz = clk_ll_xtal_load_freq_mhz();
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rtc_clk_mpll_configure(xtal_freq_mhz, expt_freq / MHZ);
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s_cur_mpll_freq = clk_ll_mpll_get_freq_mhz(xtal_freq_mhz);
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} else {
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ret = ESP_ERR_INVALID_STATE;
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}
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end:
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if (real_freq != NULL) {
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*real_freq = s_cur_mpll_freq;
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}
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portEXIT_CRITICAL(&periph_spinlock);
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return ret;
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}
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#endif // SOC_CLK_MPLL_SUPPORTED
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