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bb9aa806f7
By unchecking "Place panic handler code in IRAM" in the menuconfig, the panic handlers will be placed in flash. Of course, flash cache must be activated when entering panic handlers.
244 lines
7.3 KiB
C
244 lines
7.3 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdlib.h>
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#include "esp_spi_flash.h"
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#include "esp_private/system_internal.h"
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#include "soc/soc_memory_layout.h"
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#include "soc/cpu.h"
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#include "soc/soc_caps.h"
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#include "soc/rtc.h"
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#include "hal/soc_hal.h"
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#include "hal/cpu_hal.h"
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#include "cache_err_int.h"
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#include "sdkconfig.h"
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#include "esp_rom_sys.h"
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#if CONFIG_IDF_TARGET_ESP32
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#include "esp32/dport_access.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/memprot.h"
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#elif CONFIG_IDF_TARGET_ESP32S3
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#include "esp32s3/memprot.h"
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#elif CONFIG_IDF_TARGET_ESP32C3
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#include "esp32c3/memprot.h"
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#endif
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#include "esp_private/panic_internal.h"
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#include "esp_private/panic_reason.h"
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#include "hal/wdt_types.h"
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#include "hal/wdt_hal.h"
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extern int _invalid_pc_placeholder;
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extern void esp_panic_handler(panic_info_t *);
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static wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
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void *g_exc_frames[SOC_CPU_CORES_NUM] = {NULL};
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/*
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Panic handlers; these get called when an unhandled exception occurs or the assembly-level
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task switching / interrupt code runs into an unrecoverable error. The default task stack
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overflow handler and abort handler are also in here.
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*/
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/*
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Note: The linker script will put everything in this file in IRAM/DRAM, so it also works with flash cache disabled.
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*/
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static void print_state_for_core(const void *f, int core)
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{
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/* On Xtensa (with Window ABI), register dump is not required for backtracing.
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* Don't print it on abort to reduce clutter.
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* On other architectures, register values need to be known for backtracing.
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*/
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#if defined(__XTENSA__) && defined(XCHAL_HAVE_WINDOWED)
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if (!g_panic_abort) {
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#else
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if (true) {
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#endif
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panic_print_registers(f, core);
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panic_print_str("\r\n");
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}
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panic_print_backtrace(f, core);
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}
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static void print_state(const void *f)
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{
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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int err_core = f == g_exc_frames[0] ? 0 : 1;
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#else
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int err_core = 0;
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#endif
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print_state_for_core(f, err_core);
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panic_print_str("\r\n");
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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// If there are other frame info, print them as well
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for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
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// `f` is the frame for the offending core, see note above.
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if (err_core != i && g_exc_frames[i] != NULL) {
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print_state_for_core(g_exc_frames[i], i);
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panic_print_str("\r\n");
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}
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}
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#endif
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}
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static void frame_to_panic_info(void *frame, panic_info_t *info, bool pseudo_excause)
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{
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info->core = cpu_hal_get_core_id();
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info->exception = PANIC_EXCEPTION_FAULT;
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info->details = NULL;
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info->reason = "Unknown";
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info->pseudo_excause = pseudo_excause;
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if (pseudo_excause) {
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panic_soc_fill_info(frame, info);
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} else {
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panic_arch_fill_info(frame, info);
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}
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info->state = print_state;
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info->frame = frame;
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}
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static void panic_handler(void *frame, bool pseudo_excause)
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{
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panic_info_t info = { 0 };
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/*
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* Setup environment and perform necessary architecture/chip specific
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* steps here prior to the system panic handler.
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* */
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int core_id = cpu_hal_get_core_id();
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// If multiple cores arrive at panic handler, save frames for all of them
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g_exc_frames[core_id] = frame;
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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// These are cases where both CPUs both go into panic handler. The following code ensures
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// only one core proceeds to the system panic handler.
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if (pseudo_excause) {
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#define BUSY_WAIT_IF_TRUE(b) { if (b) while(1); }
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// For WDT expiry, pause the non-offending core - offending core handles panic
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BUSY_WAIT_IF_TRUE(panic_get_cause(frame) == PANIC_RSN_INTWDT_CPU0 && core_id == 1);
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BUSY_WAIT_IF_TRUE(panic_get_cause(frame) == PANIC_RSN_INTWDT_CPU1 && core_id == 0);
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// For cache error, pause the non-offending core - offending core handles panic
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if (panic_get_cause(frame) == PANIC_RSN_CACHEERR && core_id != esp_cache_err_get_cpuid()) {
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// Only print the backtrace for the offending core in case of the cache error
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g_exc_frames[core_id] = NULL;
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while (1) {
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;
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}
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}
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}
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esp_rom_delay_us(1);
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SOC_HAL_STALL_OTHER_CORES();
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#endif
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#if CONFIG_IDF_TARGET_ESP32
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esp_dport_access_int_abort();
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#endif
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if (esp_cpu_in_ocd_debug_mode()) {
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#if __XTENSA__
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if (!(esp_ptr_executable(cpu_ll_pc_to_ptr(panic_get_address(frame))) && (panic_get_address(frame) & 0xC0000000U))) {
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/* Xtensa ABI sets the 2 MSBs of the PC according to the windowed call size
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* Incase the PC is invalid, GDB will fail to translate addresses to function names
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* Hence replacing the PC to a placeholder address in case of invalid PC
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*/
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panic_set_address(frame, (uint32_t)&_invalid_pc_placeholder);
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}
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#endif
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if (panic_get_cause(frame) == PANIC_RSN_INTWDT_CPU0
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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|| panic_get_cause(frame) == PANIC_RSN_INTWDT_CPU1
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#endif
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) {
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wdt_hal_write_protect_disable(&wdt0_context);
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wdt_hal_handle_intr(&wdt0_context);
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wdt_hal_write_protect_enable(&wdt0_context);
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}
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}
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// Convert architecture exception frame into abstracted panic info
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frame_to_panic_info(frame, &info, pseudo_excause);
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// Call the system panic handler
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esp_panic_handler(&info);
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}
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/**
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* This function must always be in IRAM as it is required to
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* re-enable the flash cache.
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*/
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static void IRAM_ATTR panic_enable_cache(void) {
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int core_id = cpu_hal_get_core_id();
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if (!spi_flash_cache_enabled()) {
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#ifdef CONFIG_IDF_TARGET_ESP32
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esp_dport_access_int_abort();
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#endif
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spi_flash_enable_cache(core_id);
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}
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}
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void IRAM_ATTR panicHandler(void *frame)
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{
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panic_enable_cache();
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// This panic handler gets called for when the double exception vector,
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// kernel exception vector gets used; as well as handling interrupt-based
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// faults cache error, wdt expiry. EXCAUSE register gets written with
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// one of PANIC_RSN_* values.
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panic_handler(frame, true);
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}
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void IRAM_ATTR xt_unhandled_exception(void *frame)
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{
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panic_enable_cache();
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panic_handler(frame, false);
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}
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void __attribute__((noreturn)) panic_restart(void)
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{
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bool digital_reset_needed = false;
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#ifdef CONFIG_IDF_TARGET_ESP32
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// On the ESP32, cache error status can only be cleared by system reset
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if (esp_cache_err_get_cpuid() != -1) {
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digital_reset_needed = true;
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}
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#endif
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#if CONFIG_ESP_SYSTEM_CONFIG_MEMPROT_FEATURE
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if (esp_memprot_is_intr_ena_any() || esp_memprot_is_locked_any()) {
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digital_reset_needed = true;
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}
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#endif
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if (digital_reset_needed) {
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esp_restart_noos_dig();
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}
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esp_restart_noos();
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}
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