esp-idf/components/riscv
Omar Chebib e5155c2a54 fix(riscv): fix a bug in FPU exception handling
On the ESP32-P4, it is possible to have an exception because of an FPU instruction
while EXT_ILL CSR is not zero and its FPU bit is not set.
2023-11-15 18:58:30 +08:00
..
include feat(wdt): add multicore support for WDTs on RISCV 2023-10-23 18:26:08 +08:00
CMakeLists.txt fix(esp32p4): Fixed interrupt handling to use the CLIC controller 2023-08-31 12:16:08 +08:00
instruction_decode.c interrupt: filter out reserved int number by decoding risc-v JAL instruction 2021-01-05 15:39:46 +08:00
interrupt.c fix(esp32p4): Fixed interrupt handling to use the CLIC controller 2023-08-31 12:16:08 +08:00
linker.lf riscv: moved some interrupt functions from IRAM to flash 2023-04-10 12:21:11 +08:00
project_include.cmake build: Adds support for universal Clang toolchain 2022-11-23 13:25:16 +03:00
vectors_clic.S feat(esp_system): Support IPC_ISR for ESP32P4 2023-09-15 23:38:12 +08:00
vectors_intc.S fix(esp32p4): Fixed interrupt handling to use the CLIC controller 2023-08-31 12:16:08 +08:00
vectors.S fix(riscv): fix a bug in FPU exception handling 2023-11-15 18:58:30 +08:00