mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
605 lines
21 KiB
C
605 lines
21 KiB
C
/*
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* SPDX-FileCopyrightText: 2016-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <esp_types.h>
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#include <stdlib.h>
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#include <ctype.h>
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#include <string.h>
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#include "sdkconfig.h"
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#include "esp_intr_alloc.h"
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#include "esp_log.h"
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#include "esp_pm.h"
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#include "esp_check.h"
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#include "esp_heap_caps.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/semphr.h"
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#include "freertos/timers.h"
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#include "freertos/ringbuf.h"
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#include "esp_private/periph_ctrl.h"
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#include "esp_private/adc_private.h"
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#include "esp_private/adc_share_hw_ctrl.h"
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#include "esp_private/sar_periph_ctrl.h"
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#include "esp_clk_tree.h"
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#include "driver/gpio.h"
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#include "esp_adc/adc_continuous.h"
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#include "hal/adc_types.h"
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#include "hal/adc_hal.h"
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#include "hal/dma_types.h"
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#include "esp_memory_utils.h"
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#include "adc_continuous_internal.h"
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//For DMA
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#if SOC_GDMA_SUPPORTED
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#include "esp_private/gdma.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "hal/spi_types.h"
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#include "esp_private/spi_common_internal.h"
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#elif CONFIG_IDF_TARGET_ESP32
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#include "hal/i2s_types.h"
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#include "driver/i2s_types.h"
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#include "soc/i2s_periph.h"
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#include "esp_private/i2s_platform.h"
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#endif
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static const char *ADC_TAG = "adc_continuous";
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#define ADC_GET_IO_NUM(periph, channel) (adc_channel_io_map[periph][channel])
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extern portMUX_TYPE rtc_spinlock; //TODO: Will be placed in the appropriate position after the rtc module is finished.
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#define ADC_ENTER_CRITICAL() portENTER_CRITICAL(&rtc_spinlock)
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#define ADC_EXIT_CRITICAL() portEXIT_CRITICAL(&rtc_spinlock)
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#define INTERNAL_BUF_NUM 5
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/*---------------------------------------------------------------
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ADC Continuous Read Mode (via DMA)
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---------------------------------------------------------------*/
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//Function to address transaction
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static bool s_adc_dma_intr(adc_continuous_ctx_t *adc_digi_ctx);
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#if SOC_GDMA_SUPPORTED
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static bool adc_dma_in_suc_eof_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data);
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#else
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static void adc_dma_intr_handler(void *arg);
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#endif
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static int8_t adc_digi_get_io_num(adc_unit_t adc_unit, uint8_t adc_channel)
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{
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assert(adc_unit <= SOC_ADC_PERIPH_NUM);
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uint8_t adc_n = (adc_unit == ADC_UNIT_1) ? 0 : 1;
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return adc_channel_io_map[adc_n][adc_channel];
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}
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static esp_err_t adc_digi_gpio_init(adc_unit_t adc_unit, uint16_t channel_mask)
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{
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esp_err_t ret = ESP_OK;
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uint64_t gpio_mask = 0;
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uint32_t n = 0;
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int8_t io = 0;
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while (channel_mask) {
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if (channel_mask & 0x1) {
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io = adc_digi_get_io_num(adc_unit, n);
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if (io < 0) {
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return ESP_ERR_INVALID_ARG;
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}
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gpio_mask |= BIT64(io);
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}
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channel_mask = channel_mask >> 1;
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n++;
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}
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gpio_config_t cfg = {
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.pin_bit_mask = gpio_mask,
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.mode = GPIO_MODE_DISABLE,
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};
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ret = gpio_config(&cfg);
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return ret;
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}
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esp_err_t adc_continuous_new_handle(const adc_continuous_handle_cfg_t *hdl_config, adc_continuous_handle_t *ret_handle)
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{
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esp_err_t ret = ESP_OK;
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ESP_RETURN_ON_FALSE((hdl_config->conv_frame_size % SOC_ADC_DIGI_DATA_BYTES_PER_CONV == 0), ESP_ERR_INVALID_ARG, ADC_TAG, "conv_frame_size should be in multiples of `SOC_ADC_DIGI_DATA_BYTES_PER_CONV`");
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adc_continuous_ctx_t *adc_ctx = heap_caps_calloc(1, sizeof(adc_continuous_ctx_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
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if (adc_ctx == NULL) {
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ret = ESP_ERR_NO_MEM;
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goto cleanup;
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}
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//ringbuffer storage/struct buffer
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adc_ctx->ringbuf_storage = heap_caps_calloc(1, hdl_config->max_store_buf_size, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
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adc_ctx->ringbuf_struct = heap_caps_calloc(1, sizeof(StaticRingbuffer_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
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if (!adc_ctx->ringbuf_storage || !adc_ctx->ringbuf_struct) {
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ret = ESP_ERR_NO_MEM;
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goto cleanup;
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}
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//ringbuffer
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adc_ctx->ringbuf_hdl = xRingbufferCreateStatic(hdl_config->max_store_buf_size, RINGBUF_TYPE_BYTEBUF, adc_ctx->ringbuf_storage, adc_ctx->ringbuf_struct);
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if (!adc_ctx->ringbuf_hdl) {
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ret = ESP_ERR_NO_MEM;
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goto cleanup;
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}
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//malloc internal buffer used by DMA
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adc_ctx->rx_dma_buf = heap_caps_calloc(1, hdl_config->conv_frame_size * INTERNAL_BUF_NUM, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA);
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if (!adc_ctx->rx_dma_buf) {
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ret = ESP_ERR_NO_MEM;
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goto cleanup;
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}
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//malloc dma descriptor
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adc_ctx->hal.rx_desc = heap_caps_calloc(1, (sizeof(dma_descriptor_t)) * INTERNAL_BUF_NUM, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA);
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if (!adc_ctx->hal.rx_desc) {
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ret = ESP_ERR_NO_MEM;
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goto cleanup;
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}
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//malloc pattern table
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adc_ctx->hal_digi_ctrlr_cfg.adc_pattern = calloc(1, SOC_ADC_PATT_LEN_MAX * sizeof(adc_digi_pattern_config_t));
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if (!adc_ctx->hal_digi_ctrlr_cfg.adc_pattern) {
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ret = ESP_ERR_NO_MEM;
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goto cleanup;
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}
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#if CONFIG_PM_ENABLE
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ret = esp_pm_lock_create(ESP_PM_APB_FREQ_MAX, 0, "adc_dma", &adc_ctx->pm_lock);
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if (ret != ESP_OK) {
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goto cleanup;
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}
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#endif //CONFIG_PM_ENABLE
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#if SOC_GDMA_SUPPORTED
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//alloc rx gdma channel
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gdma_channel_alloc_config_t rx_alloc_config = {
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.direction = GDMA_CHANNEL_DIRECTION_RX,
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};
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ret = gdma_new_channel(&rx_alloc_config, &adc_ctx->rx_dma_channel);
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if (ret != ESP_OK) {
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goto cleanup;
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}
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gdma_connect(adc_ctx->rx_dma_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_ADC, 0));
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gdma_strategy_config_t strategy_config = {
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.auto_update_desc = true,
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.owner_check = true
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};
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gdma_apply_strategy(adc_ctx->rx_dma_channel, &strategy_config);
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gdma_rx_event_callbacks_t cbs = {
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.on_recv_eof = adc_dma_in_suc_eof_callback
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};
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gdma_register_rx_event_callbacks(adc_ctx->rx_dma_channel, &cbs, adc_ctx);
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int dma_chan;
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gdma_get_channel_id(adc_ctx->rx_dma_channel, &dma_chan);
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#elif CONFIG_IDF_TARGET_ESP32S2
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//ADC utilises SPI3 DMA on ESP32S2
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bool spi_success = false;
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uint32_t dma_chan = 0;
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spi_success = spicommon_periph_claim(SPI3_HOST, "adc");
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ret = spicommon_dma_chan_alloc(SPI3_HOST, SPI_DMA_CH_AUTO, &dma_chan, &dma_chan);
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if (ret == ESP_OK) {
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adc_ctx->spi_host = SPI3_HOST;
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}
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if (!spi_success || (adc_ctx->spi_host != SPI3_HOST)) {
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goto cleanup;
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}
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ret = esp_intr_alloc(spicommon_irqdma_source_for_host(adc_ctx->spi_host), ESP_INTR_FLAG_IRAM, adc_dma_intr_handler,
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(void *)adc_ctx, &adc_ctx->dma_intr_hdl);
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if (ret != ESP_OK) {
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goto cleanup;
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}
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#elif CONFIG_IDF_TARGET_ESP32
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//ADC utilises I2S0 DMA on ESP32
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uint32_t dma_chan = 0;
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ret = i2s_platform_acquire_occupation(I2S_NUM_0, "adc");
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if (ret != ESP_OK) {
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ret = ESP_ERR_NOT_FOUND;
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goto cleanup;
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}
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adc_ctx->i2s_host = I2S_NUM_0;
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ret = esp_intr_alloc(i2s_periph_signal[adc_ctx->i2s_host].irq, ESP_INTR_FLAG_IRAM, adc_dma_intr_handler,
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(void *)adc_ctx, &adc_ctx->dma_intr_hdl);
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if (ret != ESP_OK) {
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goto cleanup;
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}
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#endif
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adc_hal_dma_config_t config = {
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#if SOC_GDMA_SUPPORTED
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.dev = (void *)GDMA_LL_GET_HW(0),
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#elif CONFIG_IDF_TARGET_ESP32S2
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.dev = (void *)SPI_LL_GET_HW(adc_ctx->spi_host),
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#elif CONFIG_IDF_TARGET_ESP32
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.dev = (void *)I2S_LL_GET_HW(adc_ctx->i2s_host),
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#endif
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.desc_max_num = INTERNAL_BUF_NUM,
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.dma_chan = dma_chan,
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.eof_num = hdl_config->conv_frame_size / SOC_ADC_DIGI_DATA_BYTES_PER_CONV
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};
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adc_hal_dma_ctx_config(&adc_ctx->hal, &config);
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adc_ctx->fsm = ADC_FSM_INIT;
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*ret_handle = adc_ctx;
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//enable ADC digital part
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periph_module_enable(PERIPH_SARADC_MODULE);
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//reset ADC digital part
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periph_module_reset(PERIPH_SARADC_MODULE);
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#if SOC_ADC_CALIBRATION_V1_SUPPORTED
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adc_hal_calibration_init(ADC_UNIT_1);
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adc_hal_calibration_init(ADC_UNIT_2);
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#endif //#if SOC_ADC_CALIBRATION_V1_SUPPORTED
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return ret;
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cleanup:
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adc_continuous_deinit(adc_ctx);
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return ret;
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}
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#if SOC_GDMA_SUPPORTED
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static IRAM_ATTR bool adc_dma_in_suc_eof_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data)
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{
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assert(event_data);
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adc_continuous_ctx_t *ctx = (adc_continuous_ctx_t *)user_data;
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ctx->rx_eof_desc_addr = event_data->rx_eof_desc_addr;
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return s_adc_dma_intr(user_data);
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}
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#else
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static IRAM_ATTR void adc_dma_intr_handler(void *arg)
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{
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adc_continuous_ctx_t *ctx = (adc_continuous_ctx_t *)arg;
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bool need_yield = false;
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bool conversion_finish = adc_hal_check_event(&ctx->hal, ADC_HAL_DMA_INTR_MASK);
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if (conversion_finish) {
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adc_hal_digi_clr_intr(&ctx->hal, ADC_HAL_DMA_INTR_MASK);
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intptr_t desc_addr = adc_hal_get_desc_addr(&ctx->hal);
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ctx->rx_eof_desc_addr = desc_addr;
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need_yield = s_adc_dma_intr(ctx);
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}
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if (need_yield) {
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portYIELD_FROM_ISR();
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}
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}
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#endif
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static IRAM_ATTR bool s_adc_dma_intr(adc_continuous_ctx_t *adc_digi_ctx)
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{
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portBASE_TYPE taskAwoken = 0;
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bool need_yield = false;
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BaseType_t ret;
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adc_hal_dma_desc_status_t status = false;
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dma_descriptor_t *current_desc = NULL;
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while (1) {
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status = adc_hal_get_reading_result(&adc_digi_ctx->hal, adc_digi_ctx->rx_eof_desc_addr, ¤t_desc);
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if (status != ADC_HAL_DMA_DESC_VALID) {
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break;
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}
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ret = xRingbufferSendFromISR(adc_digi_ctx->ringbuf_hdl, current_desc->buffer, current_desc->dw0.length, &taskAwoken);
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need_yield |= (taskAwoken == pdTRUE);
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if (adc_digi_ctx->cbs.on_conv_done) {
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adc_continuous_evt_data_t edata = {
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.conv_frame_buffer = current_desc->buffer,
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.size = current_desc->dw0.length,
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};
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if (adc_digi_ctx->cbs.on_conv_done(adc_digi_ctx, &edata, adc_digi_ctx->user_data)) {
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need_yield |= true;
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}
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}
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if (ret == pdFALSE) {
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//ringbuffer overflow
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if (adc_digi_ctx->cbs.on_pool_ovf) {
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adc_continuous_evt_data_t edata = {};
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if (adc_digi_ctx->cbs.on_pool_ovf(adc_digi_ctx, &edata, adc_digi_ctx->user_data)) {
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need_yield |= true;
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}
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}
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}
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}
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if (status == ADC_HAL_DMA_DESC_NULL) {
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//start next turns of dma operation
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adc_hal_digi_start(&adc_digi_ctx->hal, adc_digi_ctx->rx_dma_buf);
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}
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return need_yield;
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}
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esp_err_t adc_continuous_start(adc_continuous_handle_t handle)
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{
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ESP_RETURN_ON_FALSE(handle, ESP_ERR_INVALID_STATE, ADC_TAG, "The driver isn't initialised");
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ESP_RETURN_ON_FALSE(handle->fsm == ADC_FSM_INIT, ESP_ERR_INVALID_STATE, ADC_TAG, "ADC continuous mode isn't in the init state, it's started already");
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if (handle->pm_lock) {
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ESP_RETURN_ON_ERROR(esp_pm_lock_acquire(handle->pm_lock), ADC_TAG, "acquire pm_lock failed");
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}
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handle->fsm = ADC_FSM_STARTED;
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sar_periph_ctrl_adc_continuous_power_acquire();
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//reset flags
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if (handle->use_adc1) {
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adc_lock_acquire(ADC_UNIT_1);
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}
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if (handle->use_adc2) {
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adc_lock_acquire(ADC_UNIT_2);
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}
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#if SOC_ADC_CALIBRATION_V1_SUPPORTED
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if (handle->use_adc1) {
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adc_set_hw_calibration_code(ADC_UNIT_1, handle->adc1_atten);
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}
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if (handle->use_adc2) {
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adc_set_hw_calibration_code(ADC_UNIT_2, handle->adc2_atten);
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}
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#endif //#if SOC_ADC_CALIBRATION_V1_SUPPORTED
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#if SOC_ADC_ARBITER_SUPPORTED
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if (handle->use_adc2) {
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adc_arbiter_t config = ADC_ARBITER_CONFIG_DEFAULT();
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adc_hal_arbiter_config(&config);
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}
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#endif //#if SOC_ADC_ARBITER_SUPPORTED
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if (handle->use_adc1) {
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adc_hal_set_controller(ADC_UNIT_1, ADC_HAL_CONTINUOUS_READ_MODE);
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}
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if (handle->use_adc2) {
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adc_hal_set_controller(ADC_UNIT_2, ADC_HAL_CONTINUOUS_READ_MODE);
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}
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adc_hal_digi_init(&handle->hal);
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adc_hal_digi_controller_config(&handle->hal, &handle->hal_digi_ctrlr_cfg);
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//start conversion
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adc_hal_digi_start(&handle->hal, handle->rx_dma_buf);
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return ESP_OK;
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}
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esp_err_t adc_continuous_stop(adc_continuous_handle_t handle)
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{
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ESP_RETURN_ON_FALSE(handle, ESP_ERR_INVALID_STATE, ADC_TAG, "The driver isn't initialised");
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ESP_RETURN_ON_FALSE(handle->fsm == ADC_FSM_STARTED, ESP_ERR_INVALID_STATE, ADC_TAG, "The driver is already stopped");
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handle->fsm = ADC_FSM_INIT;
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//disable the in suc eof intrrupt
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adc_hal_digi_dis_intr(&handle->hal, ADC_HAL_DMA_INTR_MASK);
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//clear the in suc eof interrupt
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adc_hal_digi_clr_intr(&handle->hal, ADC_HAL_DMA_INTR_MASK);
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//stop ADC
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adc_hal_digi_stop(&handle->hal);
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adc_hal_digi_deinit(&handle->hal);
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if (handle->use_adc2) {
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adc_lock_release(ADC_UNIT_2);
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}
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if (handle->use_adc1) {
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adc_lock_release(ADC_UNIT_1);
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}
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sar_periph_ctrl_adc_continuous_power_release();
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//release power manager lock
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if (handle->pm_lock) {
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ESP_RETURN_ON_ERROR(esp_pm_lock_release(handle->pm_lock), ADC_TAG, "release pm_lock failed");
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}
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return ESP_OK;
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}
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esp_err_t adc_continuous_read(adc_continuous_handle_t handle, uint8_t *buf, uint32_t length_max, uint32_t *out_length, uint32_t timeout_ms)
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{
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ESP_RETURN_ON_FALSE(handle, ESP_ERR_INVALID_STATE, ADC_TAG, "The driver isn't initialised");
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ESP_RETURN_ON_FALSE(handle->fsm == ADC_FSM_STARTED, ESP_ERR_INVALID_STATE, ADC_TAG, "The driver is already stopped");
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TickType_t ticks_to_wait;
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esp_err_t ret = ESP_OK;
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uint8_t *data = NULL;
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size_t size = 0;
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ticks_to_wait = timeout_ms / portTICK_PERIOD_MS;
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if (timeout_ms == ADC_MAX_DELAY) {
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ticks_to_wait = portMAX_DELAY;
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}
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data = xRingbufferReceiveUpTo(handle->ringbuf_hdl, &size, ticks_to_wait, length_max);
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if (!data) {
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ESP_LOGV(ADC_TAG, "No data, increase timeout");
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ret = ESP_ERR_TIMEOUT;
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*out_length = 0;
|
|
return ret;
|
|
}
|
|
|
|
memcpy(buf, data, size);
|
|
vRingbufferReturnItem(handle->ringbuf_hdl, data);
|
|
assert((size % 4) == 0);
|
|
*out_length = size;
|
|
|
|
return ret;
|
|
}
|
|
|
|
esp_err_t adc_continuous_deinit(adc_continuous_handle_t handle)
|
|
{
|
|
ESP_RETURN_ON_FALSE(handle, ESP_ERR_INVALID_STATE, ADC_TAG, "The driver isn't initialised");
|
|
ESP_RETURN_ON_FALSE(handle->fsm == ADC_FSM_INIT, ESP_ERR_INVALID_STATE, ADC_TAG, "The driver is still running");
|
|
|
|
if (handle->ringbuf_hdl) {
|
|
vRingbufferDelete(handle->ringbuf_hdl);
|
|
handle->ringbuf_hdl = NULL;
|
|
free(handle->ringbuf_storage);
|
|
free(handle->ringbuf_struct);
|
|
}
|
|
|
|
if (handle->pm_lock) {
|
|
esp_pm_lock_delete(handle->pm_lock);
|
|
}
|
|
|
|
free(handle->rx_dma_buf);
|
|
free(handle->hal.rx_desc);
|
|
free(handle->hal_digi_ctrlr_cfg.adc_pattern);
|
|
#if SOC_GDMA_SUPPORTED
|
|
gdma_disconnect(handle->rx_dma_channel);
|
|
gdma_del_channel(handle->rx_dma_channel);
|
|
#elif CONFIG_IDF_TARGET_ESP32S2
|
|
esp_intr_free(handle->dma_intr_hdl);
|
|
spicommon_dma_chan_free(handle->spi_host);
|
|
spicommon_periph_free(handle->spi_host);
|
|
#elif CONFIG_IDF_TARGET_ESP32
|
|
esp_intr_free(handle->dma_intr_hdl);
|
|
i2s_platform_release_occupation(handle->i2s_host);
|
|
#endif
|
|
free(handle);
|
|
handle = NULL;
|
|
|
|
periph_module_disable(PERIPH_SARADC_MODULE);
|
|
|
|
return ESP_OK;
|
|
}
|
|
|
|
/*---------------------------------------------------------------
|
|
Digital controller setting
|
|
---------------------------------------------------------------*/
|
|
esp_err_t adc_continuous_config(adc_continuous_handle_t handle, const adc_continuous_config_t *config)
|
|
{
|
|
ESP_RETURN_ON_FALSE(handle, ESP_ERR_INVALID_STATE, ADC_TAG, "The driver isn't initialised");
|
|
ESP_RETURN_ON_FALSE(handle->fsm == ADC_FSM_INIT, ESP_ERR_INVALID_STATE, ADC_TAG, "ADC continuous mode isn't in the init state, it's started already");
|
|
|
|
//Pattern related check
|
|
ESP_RETURN_ON_FALSE(config->pattern_num <= SOC_ADC_PATT_LEN_MAX, ESP_ERR_INVALID_ARG, ADC_TAG, "Max pattern num is %d", SOC_ADC_PATT_LEN_MAX);
|
|
for (int i = 0; i < config->pattern_num; i++) {
|
|
ESP_RETURN_ON_FALSE((config->adc_pattern[i].bit_width >= SOC_ADC_DIGI_MIN_BITWIDTH && config->adc_pattern->bit_width <= SOC_ADC_DIGI_MAX_BITWIDTH), ESP_ERR_INVALID_ARG, ADC_TAG, "ADC bitwidth not supported");
|
|
}
|
|
|
|
for (int i = 0; i < config->pattern_num; i++) {
|
|
#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3
|
|
//we add this error log to hint users what happened
|
|
if (SOC_ADC_DIG_SUPPORTED_UNIT(config->adc_pattern[i].unit) == 0) {
|
|
ESP_LOGE(ADC_TAG, "ADC2 continuous mode is no longer supported, please use ADC1. Search for errata on espressif website for more details. You can enable CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3 to force use ADC2");
|
|
}
|
|
#endif //CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3
|
|
|
|
#if !CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3
|
|
/**
|
|
* On all continuous mode supported chips, we will always check the unit to see if it's a continuous mode supported unit.
|
|
* However, on ESP32C3 and ESP32S3, we will jump this check, if `CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3` is enabled.
|
|
*/
|
|
ESP_RETURN_ON_FALSE(SOC_ADC_DIG_SUPPORTED_UNIT(config->adc_pattern[i].unit), ESP_ERR_INVALID_ARG, ADC_TAG, "Only support using ADC1 DMA mode");
|
|
#endif //#if !CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3
|
|
}
|
|
|
|
ESP_RETURN_ON_FALSE(config->sample_freq_hz <= SOC_ADC_SAMPLE_FREQ_THRES_HIGH && config->sample_freq_hz >= SOC_ADC_SAMPLE_FREQ_THRES_LOW, ESP_ERR_INVALID_ARG, ADC_TAG, "ADC sampling frequency out of range");
|
|
|
|
#if CONFIG_IDF_TARGET_ESP32
|
|
ESP_RETURN_ON_FALSE(config->format == ADC_DIGI_OUTPUT_FORMAT_TYPE1, ESP_ERR_INVALID_ARG, ADC_TAG, "Please use type1");
|
|
#elif CONFIG_IDF_TARGET_ESP32S2
|
|
if (config->conv_mode == ADC_CONV_BOTH_UNIT || config->conv_mode == ADC_CONV_ALTER_UNIT) {
|
|
ESP_RETURN_ON_FALSE(config->format == ADC_DIGI_OUTPUT_FORMAT_TYPE2, ESP_ERR_INVALID_ARG, ADC_TAG, "Please use type2");
|
|
} else if (config->conv_mode == ADC_CONV_SINGLE_UNIT_1 || config->conv_mode == ADC_CONV_SINGLE_UNIT_2) {
|
|
ESP_RETURN_ON_FALSE(config->format == ADC_DIGI_OUTPUT_FORMAT_TYPE1, ESP_ERR_INVALID_ARG, ADC_TAG, "Please use type1");
|
|
}
|
|
#else
|
|
ESP_RETURN_ON_FALSE(config->format == ADC_DIGI_OUTPUT_FORMAT_TYPE2, ESP_ERR_INVALID_ARG, ADC_TAG, "Please use type2");
|
|
#endif
|
|
|
|
uint32_t clk_src_freq_hz = 0;
|
|
esp_clk_tree_src_get_freq_hz(ADC_DIGI_CLK_SRC_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz);
|
|
|
|
handle->hal_digi_ctrlr_cfg.adc_pattern_len = config->pattern_num;
|
|
handle->hal_digi_ctrlr_cfg.sample_freq_hz = config->sample_freq_hz;
|
|
handle->hal_digi_ctrlr_cfg.conv_mode = config->conv_mode;
|
|
memcpy(handle->hal_digi_ctrlr_cfg.adc_pattern, config->adc_pattern, config->pattern_num * sizeof(adc_digi_pattern_config_t));
|
|
handle->hal_digi_ctrlr_cfg.clk_src = ADC_DIGI_CLK_SRC_DEFAULT;
|
|
handle->hal_digi_ctrlr_cfg.clk_src_freq_hz = clk_src_freq_hz;
|
|
|
|
const int atten_uninitialized = 999;
|
|
handle->adc1_atten = atten_uninitialized;
|
|
handle->adc2_atten = atten_uninitialized;
|
|
handle->use_adc1 = 0;
|
|
handle->use_adc2 = 0;
|
|
uint32_t adc1_chan_mask = 0;
|
|
uint32_t adc2_chan_mask = 0;
|
|
for (int i = 0; i < config->pattern_num; i++) {
|
|
const adc_digi_pattern_config_t *pat = &config->adc_pattern[i];
|
|
if (pat->unit == ADC_UNIT_1) {
|
|
handle->use_adc1 = 1;
|
|
adc1_chan_mask |= BIT(pat->channel);
|
|
|
|
if (handle->adc1_atten == atten_uninitialized) {
|
|
handle->adc1_atten = pat->atten;
|
|
} else if (handle->adc1_atten != pat->atten) {
|
|
return ESP_ERR_INVALID_ARG;
|
|
}
|
|
} else if (pat->unit == ADC_UNIT_2) {
|
|
handle->use_adc2 = 1;
|
|
adc2_chan_mask |= BIT(pat->channel);
|
|
|
|
if (handle->adc2_atten == atten_uninitialized) {
|
|
handle->adc2_atten = pat->atten;
|
|
} else if (handle->adc2_atten != pat->atten) {
|
|
return ESP_ERR_INVALID_ARG;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (handle->use_adc1) {
|
|
adc_digi_gpio_init(ADC_UNIT_1, adc1_chan_mask);
|
|
}
|
|
if (handle->use_adc2) {
|
|
adc_digi_gpio_init(ADC_UNIT_2, adc2_chan_mask);
|
|
}
|
|
|
|
return ESP_OK;
|
|
}
|
|
|
|
esp_err_t adc_continuous_register_event_callbacks(adc_continuous_handle_t handle, const adc_continuous_evt_cbs_t *cbs, void *user_data)
|
|
{
|
|
ESP_RETURN_ON_FALSE(handle && cbs, ESP_ERR_INVALID_ARG, ADC_TAG, "invalid argument");
|
|
ESP_RETURN_ON_FALSE(handle->fsm == ADC_FSM_INIT, ESP_ERR_INVALID_STATE, ADC_TAG, "ADC continuous mode isn't in the init state, it's started already");
|
|
|
|
#if CONFIG_ADC_CONTINUOUS_ISR_IRAM_SAFE
|
|
if (cbs->on_conv_done) {
|
|
ESP_RETURN_ON_FALSE(esp_ptr_in_iram(cbs->on_conv_done), ESP_ERR_INVALID_ARG, ADC_TAG, "on_conv_done callback not in IRAM");
|
|
}
|
|
if (cbs->on_pool_ovf) {
|
|
ESP_RETURN_ON_FALSE(esp_ptr_in_iram(cbs->on_pool_ovf), ESP_ERR_INVALID_ARG, ADC_TAG, "on_pool_ovf callback not in IRAM");
|
|
}
|
|
#endif
|
|
|
|
handle->cbs.on_conv_done = cbs->on_conv_done;
|
|
handle->cbs.on_pool_ovf = cbs->on_pool_ovf;
|
|
handle->user_data = user_data;
|
|
|
|
return ESP_OK;
|
|
}
|
|
|
|
esp_err_t adc_continuous_io_to_channel(int io_num, adc_unit_t *unit_id, adc_channel_t *channel)
|
|
{
|
|
return adc_io_to_channel(io_num, unit_id, channel);
|
|
}
|
|
|
|
esp_err_t adc_continuous_channel_to_io(adc_unit_t unit_id, adc_channel_t channel, int *io_num)
|
|
{
|
|
return adc_channel_to_io(unit_id, channel, io_num);
|
|
}
|