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f244a8b209
This commit fixes an issue where in the ULP RISC-V I2C example causes a spurious wakeup of the main CPU because of a Trap signal when the ULP core does not meet the wakeup threshold values. This was due to the fact that the RTC_CNTL_COCPU_DONE signal was being set before the RTC_CNTL_COCPU_SHUT_RESET_EN signal which was causing the the ULP RISC-V core to not reset properly on each cycle. Closes https://github.com/espressif/esp-idf/issues/10301 |
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.. | ||
cmake | ||
ld | ||
test_apps | ||
ulp_common | ||
ulp_fsm | ||
ulp_riscv | ||
.build-test-rules.yml | ||
CMakeLists.txt | ||
component_ulp_common.cmake | ||
esp32ulp_mapgen.py | ||
Kconfig | ||
project_include.cmake | ||
sdkconfig.rename.esp32 | ||
sdkconfig.rename.esp32s2 |