alex/esp-idf
alex/esp-idf
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9cb32917a5
esp-idf/components/soc
History
KonstantinKondrashov 9cb32917a5 feat(efuse): Add flash&psram efuses for S3
2024-02-22 11:49:28 +02:00
..
esp32 ci(mbedtls): added a test for the mbedtls_internal_shaX_process API 2023-12-05 16:54:31 +05:30
esp32c3 fix(i2s): fixed incorrect reg base name on C3 2024-01-26 18:45:19 +08:00
esp32h2 fix(i2s): fixed incorrect reg base name on C3 2024-01-26 18:45:19 +08:00
esp32s2 fix(spi): Correct REG_SPI_BASE(i) macro for all targets 2023-12-22 15:08:45 +08:00
esp32s3 feat(efuse): Add flash&psram efuses for S3 2024-02-22 11:49:28 +02:00
include/soc fix(esp_hw_support): Fix different signed comparison in esp_ptr_in_drom 2023-12-11 10:21:27 +05:30
CMakeLists.txt Merge branch 'refactor/move_ldscript_to_soc' into 'master' 2021-07-23 11:54:56 +00:00
component.mk soc: move peripheral linker scripts out of target component 2021-07-22 12:55:01 +08:00
linker.lf soc: move implementations to esp_hw_support 2020-10-28 22:38:50 +08:00
lldesc.c crypto: initial S3 Beta 3 bringup and testing for SHA/AES/RSA/flash enc 2021-05-18 11:25:41 +08:00
README.md soc: descriptive part occupy whole component 2020-10-28 07:21:29 +08:00
soc_include_legacy_warn.c Whitespace: Automated whitespace fixes (large commit) 2020-11-11 07:36:35 +00:00

README.md

soc

The soc component provides hardware description for targets supported by ESP-IDF.

- `xxx_reg.h`   - defines registers related to the hardware
- `xxx_struct.h` - hardware description in C `struct`
- `xxx_channel.h` - definitions for hardware with multiple channels
- `xxx_caps.h`  - features/capabilities of the hardware
- `xxx_pins.h`  - pin definitions
- `xxx_periph.h/*.c`  - includes all headers related to a peripheral; declaration and definition of IO mapping for that hardware