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esp-idf/examples/system/ulp/lp_core/interrupt
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Marius Vikhammer aae3aa5e5f feat(lp-core): bringup lp-core for C5 MP 
LP-Core is now able to boot and run on C5 MP chip.
2024-06-19 09:18:47 +08:00
..
main feat(ulp): support interrupts for C6/P4 LP core 2024-04-28 17:03:23 +08:00
CMakeLists.txt feat(ulp): support interrupts for C6/P4 LP core 2024-04-28 17:03:23 +08:00
pytest_lp_core_intr.py feat(ulp): support interrupts for C6/P4 LP core 2024-04-28 17:03:23 +08:00
README.md feat(lp-core): bringup lp-core for C5 MP 2024-06-19 09:18:47 +08:00
sdkconfig.defaults feat(ulp): support interrupts for C6/P4 LP core 2024-04-28 17:03:23 +08:00

README.md

Supported Targets ESP32-C5 ESP32-C6 ESP32-P4

LP-Core example with interrupt triggered from HP-Core:

This example demonstrates how to program the ULP coprocessor to receive an interrupt triggered by the HP-Core

ULP program written in C can be found across lp_core/main.c. The build system compiles and links this program, converts it into binary format, and embeds it into the .rodata section of the ESP-IDF application.

At runtime, the application running inside the main CPU loads ULP program into the RTC_SLOW_MEM memory region using ulp_lp_core_load_binary function. The main code then configures the ULP and starts the coprocessor by using ulp_lp_core_run. Once the ULP program is started, it runs continuously, waiting for interrupts. The main program will periodically trigger interrupts on the LP-Core.

After triggering a certain amount of interrupts, the main core will read and print the number of interrupts received as reported by the LP-Core.

Example output

LP core loaded with firmware and running successfully
Triggered 10 interrupts on the LP-Core, LP-Core received 10 interrupts