Marius Vikhammer 9a6de4cb3e fix(panic): fixed cache error being reported as illegal instruction ... On riscv chips accessing cache mapped memory regions over the ibus would result in an illegal instructions exception triggering faster than the cache error interrupt/exception. Added a cache error check in the panic handler, if any cache errors are active the panic handler will now report a cache error, even if the trigger exception was a illegal instructions.		2023-12-04 10:49:00 +08:00
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include	fix(panic): fixed cache error being reported as illegal instruction	2023-12-04 10:49:00 +08:00
CMakeLists.txt	fix(esp32p4): Fixed interrupt handling to use the CLIC controller	2023-08-31 12:16:08 +08:00
instruction_decode.c	interrupt: filter out reserved int number by decoding risc-v JAL instruction	2021-01-05 15:39:46 +08:00
interrupt.c	fix(esp32p4): Fixed interrupt handling to use the CLIC controller	2023-08-31 12:16:08 +08:00
linker.lf	riscv: moved some interrupt functions from IRAM to flash	2023-04-10 12:21:11 +08:00
project_include.cmake	build: Adds support for universal Clang toolchain	2022-11-23 13:25:16 +03:00
vectors_clic.S	feat(esp_system): Support IPC_ISR for ESP32P4	2023-09-15 23:38:12 +08:00
vectors_intc.S	fix(esp32p4): Fixed interrupt handling to use the CLIC controller	2023-08-31 12:16:08 +08:00
vectors.S	fix(riscv): fix a bug in FPU exception handling	2023-11-14 06:55:08 +00:00