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9a6de4cb3e
On riscv chips accessing cache mapped memory regions over the ibus would result in an illegal instructions exception triggering faster than the cache error interrupt/exception. Added a cache error check in the panic handler, if any cache errors are active the panic handler will now report a cache error, even if the trigger exception was a illegal instructions. |
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.. | ||
cache_err_int.c | ||
clk.c | ||
CMakeLists.txt | ||
Kconfig.cpu | ||
Kconfig.system | ||
reset_reason.c | ||
system_internal.c |